A 6-b 1.6-Gsample/s flash ADC in 0.18-μm CMOS using averaging termination. - Peter C. S. Scholtens; Maarten Vertregt (IEEE J. Solid State Circuits, 2002)

A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. - Simon M. Louwsma; Ed J. M. van Tuijl; Maarten Vertregt; Peter C. S. Scholtens; Bram Nauta (ESSCIRC, 2004)

Assessment of the merits of CMOS technology scaling for analog circuit design. - Maarten Vertregt; Peter C. S. Scholtens (ESSCIRC, 2004)

Systematic power reduction and performance analysis of mismatch limited ADC designs. - Peter C. S. Scholtens; David Smola; Maarten Vertregt (ISLPED, 2005)