Delay analysis of neuron-MOS and capacitive threshold-logic. - Peter Celinski; Said F. Al-Sarawi; Derek Abbott (ICECS, 2000)

Low depth carry lookahead addition using charge recycling threshold logic. - Peter Celinski; Said F. Al-Sarawi; Derek Abbott; José Francisco López (ISCAS (1), 2002)

Area efficient, high speed parallel counter circuits using charge recycling threshold logic. - Peter Celinski; Derek Abbott; Sorin Dan Cotofana (ISCAS (5), 2003)

A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. - Peter Celinski; Sorin Cotofana; Derek Abbott (IWANN (2), 2003)

Logical Effort Based Design Exploration of 64-bit Adders Using a Mixed Dynamic-CMOS/Threshold-Logic Approach. - Peter Celinski; Said F. Al-Sarawi; Derek Abbott; Sorin Cotofana; Stamatis Vassiliadis (ISVLSI, 2004)

Hybrid Parallel Counters - Domino and Threshold Logic. - Troy D. Townsend; Peter Celinski; Said F. Al-Sarawi; Michael J. Liebelt (ISVLSI, 2004)

Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. - Peter Celinski; Derek Abbott; Sorin Cotofana (PATMOS, 2004)