Dynamic Time-Slot Allocation for QoS Enabled Networks on Chip. - Théodore Marescaux; B. Bricke; Peter Debacker; Vincent Nollet; Henk Corporaal (ESTIMedia, 2005)

A novel positioning technique for the 2.4GHz ISM band. - Huub Tubbax; Johan Wouters; Jan Olbrechts; Peter Debacker; Peter Spiessens; Frederic Stubbe; Johan Danneels (WPNC, 2009)

Power Estimation at Different Abstraction Levels for Wireless Baseband Processors. - Martin Palkovic; Peter Debacker; Prabhat Avasare; Steven Dupont; Tom Vander Aa (J. Low Power Electron., 2012)

A C-programmable baseband processor with inner modem implementations for LTE Cat-4/5/7 and Gbps 80MHz 4×4 802.11ac (invited). - Min Li 001; Amir Amin; Raf Appeltans; Andy Folens; Ubaid Ahmad; Hans Cappelle; Peter Debacker; Lieven Hollevoet; André Bourdoux; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (GlobalSIP, 2013)

A processor based multi-standard low-power LDPC engine for multi-Gbps wireless communication. - Meng Li 012; Frederik Naessens; Min Li 001; Peter Debacker; Claude Desset; Praveen Raghavan; Antoine Dejonghe; Liesbet Van der Perre (GlobalSIP, 2013)

An area and energy efficient half-row-paralleled layer LDPC decoder for the 802.11AD standard. - Meng Li 012; Frederik Naessens; Peter Debacker; Praveen Raghavan; Claude Desset; Min Li 001; Antoine Dejonghe; Liesbet Van der Perre (SiPS, 2013)

Computation-skip error resilient scheme for recursive CORDIC. - Yanxiang Huang; Meng Li 012; Chunshu Li; Peter Debacker; Liesbet Van der Perre (SiPS, 2014)

An energy efficient 18Gbps LDPC decoding processor for 802.11ad in 28nm CMOS. - Meng Li 012; Jan-Willem Weijers; Veerle Derudder; Ilse Vos; Maxim Rykunov; Steven Dupont; Peter Debacker; Andy Dewilde; Yanxiang Huang; Liesbet Van der Perre; Wim Van Thillo (A-SSCC, 2015)

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components. - Dimitrios Stamoulis; Simone Corbetta; Dimitrios Rodopoulos; Pieter Weckx; Peter Debacker; Brett H. Meyer; Ben Kaczer; Praveen Raghavan; Dimitrios Soudris; Francky Catthoor; Zeljko Zilic (ACM Great Lakes Symposium on VLSI, 2016)

How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? - Bon Woong Ku; Peter Debacker; Dragomir Milojevic; Praveen Raghavan; Sung Kyu Lim (ICCAD, 2016)

Physical Design Solutions to Tackle FEOL/BEOL Degradation in Gate-level Monolithic 3D ICs. - Bon Woong Ku; Peter Debacker; Dragomir Milojevic; Praveen Raghavan; Diederik Verkest; Aaron Thean; Sung Kyu Lim (ISLPED, 2016)

5nm: Has the time for a device change come? - Praveen Raghavan; Marie Garcia Bardon; Peter Debacker; P. Schuddinck; Doyoung Jang; Rogier Baert; Diederik Verkest; Aaron Voon-Yew Thean (ISQED, 2016)

Computation-skip Error Mitigation Scheme for Power Supply Voltage Scaling in Recursive Applications. - Yanxiang Huang; Meng Li 012; Chunshu Li; Peter Debacker; Liesbet Van der Perre (J. Signal Process. Syst., 2016)

Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. - Peter Debacker; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Praveen Raghavan; Lutong Wang (DAC, 2017)

IR-drop aware Design & technology co-optimization for N5 node with different device and cell height options. - Luca Mattii; Dragomir Milojevic; Peter Debacker; Yasser Sherazi; Mladen Berekovic; Praveen Raghavan (ICCAD, 2017)

Patterning Aware Design Optimization of Selective Etching in N5 and Beyond. - Yibo Lin; Peter Debacker; Darko Trivkovic; Ryoung-Han Kim; Praveen Raghavan; David Z. Pan (ICCD, 2017)

MILP-Based Optimization of 2-D Block Masks for Timing-Aware Dummy Segment Removal in Self-Aligned Multiple Patterning Layouts. - Peter Debacker; Kwangsoo Han; Andrew B. Kahng; Hyein Lee 001; Praveen Raghavan; Lutong Wang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Design Enablement of Fine Pitch Face-to-Face 3D System Integration using Die-by-Die Place & Route. - Giuliano Sisto; Peter Debacker; Rongmei Chen; Geert Van der Plas; Richard Chou; Eric Beyne; Dragomir Milojevic (3DIC, 2019)

Sub-Word Parallel Precision-Scalable MAC Engines for Efficient Embedded DNN Inference. - Linyan Mei; Mohit Dandekar; Dimitrios Rodopoulos; Jeremy Constantin; Peter Debacker; Rudy Lauwereins; Marian Verhelst (AICAS, 2019)

A Comparative Analysis on the Impact of Bank Contention in STT-MRAM and SRAM Based LLCs. - Timon Evenblij; Christian Tenllado; Manu Perumkunnil; Francky Catthoor; Sushil Sakhare; Peter Debacker; Gouri Sankar Kar; Arnaud Furnémont; Nicolas Bueno; José Ignacio Gómez Pérez (ICCD, 2019)

Low Voltage Transient RESET Kinetic Modeling of OxRRAM for Neuromorphic Applications. - Jonas Doevenspeck; Robin Degraeve; Andrea Fantini; Peter Debacker; Diederik Verkest; Rudy Lauwereins; Wim Dehaene (IRPS, 2019)

FQ-Conv: Fully Quantized Convolution for Efficient and Accurate Inference. - Bram-Ernst Verhoef; Nathan Laubeuf; Stefan Cosemans; Peter Debacker; Ioannis A. Papistas; Arindam Mallik; Diederik Verkest (CoRR, 2019)

A 22 nm, 1540 TOP/s/W, 12.1 TOP/s/mm2 in-Memory Analog Matrix-Vector-Multiplier for DNN Acceleration. - Ioannis A. Papistas; Stefan Cosemans; Bram Rooseleer; Jonas Doevenspeck; Myung Hee Na; Arindam Mallik; Peter Debacker; Diederik Verkest (CICC, 2021)

Noise tolerant ternary weight deep neural networks for analog in-memory inference. - Jonas Doevenspeck; Peter Vrancx; Nathan Laubeuf; Arindam Mallik; Peter Debacker; Diederik Verkest; Rudy Lauwereins; Wim Dehaene (IJCNN, 2021)

Design-Technology Space Exploration for Energy Efficient AiMC-Based Inference Acceleration. - Debjyoti Bhattacharjee; Nathan Laubeuf; Stefan Cosemans; Ioannis A. Papistas; Arindam Mallik; Peter Debacker; Myung Hee Na; Diederik Verkest (ISCAS, 2021)

Charge Sharing and Charge Injection A/D Converters for Analog In-Memory Computing. - Michele Caselli; Ioannis A. Papistas; Stefan Cosemans; Arindam Mallik; Peter Debacker; Diederik Verkest (NEWCAS, 2021)

Learn to Learn on Chip: Hardware-aware Meta-learning for Quantized Few-shot Learning at the Edge. - Nitish Satya Murthy; Peter Vrancx; Nathan Laubeuf; Peter Debacker; Francky Catthoor; Marian Verhelst (SEC, 2022)

Tiny ci-SAR A/D Converter for Deep Neural Networks in Analog in-Memory Computation. - Michele Caselli; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest (ISCAS, 2022)

Write-Verify Scheme for IGZO DRAM in Analog in-Memory Computing. - Michele Caselli; Subhali Subhechha; Peter Debacker; Arindam Mallik; Diederik Verkest (ISCAS, 2022)

DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC. - Kodai Ueyoshi; Ioannis A. Papistas; Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Man Shi; Qilin Zheng; Juan Sebastian Piedrahita Giraldo; Peter Vrancx; Jonas Doevenspeck; Debjyoti Bhattacharjee; Stefan Cosemans; et al. (ISSCC, 2022)

AERO: Design Space Exploration Framework for Resource-Constrained CNN Mapping on Tile-Based Accelerators. - Simei Yang; Debjyoti Bhattacharjee; Vinay B. Y. Kumar; Saikat Chatterjee; Sayandip De; Peter Debacker; Diederik Verkest; Arindam Mallik; Francky Catthoor (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Memory Devices and A/D Interfaces: Design Tradeoffs in Mixed-Signal Accelerators for Machine Learning Applications. - Michele Caselli; Peter Debacker; Andrea Boni (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Dynamic Quantization Range Control for Analog-in-Memory Neural Networks Acceleration. - Nathan Laubeuf; Jonas Doevenspeck; Ioannis A. Papistas; Michele Caselli; Stefan Cosemans; Peter Vrancx; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Francky Catthoor; Rudy Lauwereins (ACM Trans. Design Autom. Electr. Syst., 2022)

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part I: CNFET Transistor Optimization. - Rongmei Chen; Lin Chen; Jie Liang; Yuanqing Cheng; Souhir Elloumi; Jaehyun Lee; Kangwei Xu; Vihar P. Georgiev; Kai Ni 004; Peter Debacker; Asen Asenov; Aida Todri-Sanial (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Carbon Nanotube SRAM in 5-nm Technology Node Design, Optimization, and Performance Evaluation - Part II: CNT Interconnect Optimization. - Rongmei Chen; Lin Chen; Jie Liang; Yuanqing Cheng; Souhir Elloumi; Jaehyun Lee; Kangwei Xu; Vihar P. Georgiev; Kai Ni 004; Peter Debacker; Asen Asenov; Aida Todri-Sanial (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W. - Mohit Gupta 004; Stefan Cosemans; Peter Debacker; Wim Dehaene (ESSCIRC, 2023)

Optimising GPGPU Execution Through Runtime Micro-Architecture Parameter Analysis. - Giuseppe Maria Sarda; Nimish Shah; Debjyoti Bhattacharjee; Peter Debacker; Marian Verhelst (IISWC, 2023)

Demonstration of multilevel multiply accumulate operations for AiMC using engineered a-IGZO transistors-based 2T1C gain cell arrays. - Subhali Subhechha; Stefan Cosemans; Attilio Belmonte; Nouredine Rassoul; Shamin Houshmand Sharifi; Peter Debacker; Diederik Verkest; Romain Delhougne; Gouri Sankar Kar (IMW, 2023)

Evaluating the Effects of FeFET Device Variability on Charge Sharing Based AiMC Accelerator. - Swatilekha Majumdar; Stefan Cosemans; Arindam Mallik; Peter Debacker; Francky Catthoor; Jan Van Houdt (ISCAS, 2023)

DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge. - Pouya Houshmand; Giuseppe Maria Sarda; Vikram Jain; Kodai Ueyoshi; Ioannis A. Papistas; Man Shi; Qilin Zheng; Debjyoti Bhattacharjee; Arindam Mallik; Peter Debacker; Diederik Verkest; Marian Verhelst (IEEE J. Solid State Circuits, 2023)