ASIC design using the high-level synthesis system CALLAS: a case study. - Michael Koster; Martin Geiger; Peter Duzy (ICCD, 1990)

High-Level Synthesis from VHDL with Exact Timing Constraints. - A. Stoll; Peter Duzy (DAC, 1992)

The CALLAS synthesis system and its application to mechatronic ASIC design problems. - Peter Windirsch; Peter Duzy (EURO-DAC, 1993)

The Siemens high-level synthesis system CALLAS. - Jörg Biesenack; Michael Koster; Anton Langmaier; Stephane Ledeux; Sabine März; Michael Payer; Michael Pilsl; Steffen Rumler; Holger Soukup; Norbert Wehn; Peter Duzy (IEEE Trans. Very Large Scale Integr. Syst., 1993)

Scheduling of behavioral VHDL by retiming techniques. - Norbert Wehn; Jörg Biesenack; Peter Duzy; T. Langmaier; Michael Münch; Michael Pilsl; Steffen Rumler (EURO-DAC, 1994)