A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion. - Peter Figuli; Michael Hübner 001; Romuald Girardey; Falco Bapp; Thomas Bruckschlögl; Florian Thoma; Jörg Henkel; Jürgen Becker 001 (AHS, 2011)

A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. - Michael Hübner 001; Peter Figuli; Romuald Girardey; Dimitrios Soudris; Kostas Siozios; Jürgen Becker 001 (IPDPS Workshops, 2011)

On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation. - Harry Sidiropoulos; Kostas Siozios; Peter Figuli; Dimitrios Soudris; Michael Hübner 001 (IPDPS Workshops, 2012)

A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization. - Harry Sidiropoulos; Peter Figuli; Kostas Siozios; Dimitrios Soudris; Jürgen Becker 001 (FPL, 2013)

ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. - Peter Figuli; Carsten Tradowsky; Nadine Gaertner; Jürgen Becker 001 (ISSoC, 2013)

JITPR: A framework for supporting fast application's implementation onto FPGAs. - Harry Sidiropoulos; Kostas Siozios; Peter Figuli; Dimitrios Soudris; Michael Hübner 001; Jürgen Becker 001 (ACM Trans. Reconfigurable Technol. Syst., 2013)

A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. - Peter Figuli; Carsten Tradowsky; Jose Martinez; Harry Sidiropoulos; Kostas Siozios; Holger Stenschke; Dimitrios Soudris; Jürgen Becker 001 (ARC, 2015)

TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. - Kostas Siozios; Peter Figuli; Harry Sidiropoulos; Carsten Tradowsky; Dionysios Diamantopoulos; Konstantinos Maragos 001; Shalina Percy Delicia; Dimitrios Soudris; Jürgen Becker 001 (ARC, 2015)

Parametric design space exploration for optimizing QAM based high-speed communication. - Shalina Percy Delicia; George Ford; Peter Figuli; Jürgen Becker 001 (ICCC, 2015)

A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models. - Efstathios Sotiriou-Xanthopoulos; Shalina Percy Delicia; Peter Figuli; Kostas Siozios; George Economakos; Jürgen Becker 001 (SAMOS, 2015)

A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing. - Shalina Percy Delicia Figuli; Alberto Sonnino; Peter Figuli; Jürgen Becker 001 (TSP, 2016)

High-Speed Medical Imaging in 3D Ultrasound Computer Tomography. - Matthias Birk; Ernst Kretzek; Peter Figuli; Marc Weber; Jürgen Becker 001; Nicole V. Ruiter (IEEE Trans. Parallel Distributed Syst., 2016)

Parameter Sensitivity in Virtual FPGA Architectures. - Peter Figuli; Weiqiao Ding; Shalina Percy Delicia Figuli; Kostas Siozios; Dimitrios Soudris; Jürgen Becker 001 (ARC, 2017)

A reconfigurable high-speed spiral FIR filter architecture. - Shalina Percy Delicia Figuli; Peter Figuli; Jürgen Becker 001 (TSP, 2017)

AI accelerator on IBM telum processor: industrial product. - Cédric Lichtenau; Alper Buyuktosunoglu; Ramon Bertran; Peter Figuli; Christian Jacobi 002; Nikolaos Papandreou; Haris Pozidis; Anthony Saporito; Andrew Sica; Elpida Tzortzatos (ISCA, 2022)