An algebra for logic strength simulation. - Peter Flake; Philip Moorby; Gerry Musgrave (DAC, 1983)

Superlog, a unified design language for system-on-chip. - Peter Flake; Simon J. Davidmann (ASP-DAC, 2000)

One language or more?: how can we design an SoC at a system level? - Masaharu Imai; Gary Smith 001; Steven Schulz; Karen Bartleson; Daniel Gajski; Wolfgang Rosenstiel; Peter Flake; Hiroto Yasuura (ASP-DAC, 2000)

Panel: Your Core - My Problem? Integration and Verification of IP. - Gabe Moretti; Tim Hopes; Ramesh Narayanaswamy; Nanette Collins; Dave Kelf; Tom Anderson; Janick Bergeron; Ashish Dixit; Peter Flake (DAC, 2001)

SystemC and SystemVerilog: Where do They Fit? Where are They Going? - Donatella Sciuto; Grant Martin; Wolfgang Rosenstiel; Stuart Swan; Frank Ghenassia; Peter Flake; Johny Srouji (DATE, 2004)

System-level exploration tools for MPSoC designs. - Peter Flake; Simon J. Davidmann; Frank Schirrmeister (DAC, 2006)

Why SystemVeriog? - Peter Flake (FDL, 2013)

Systemc infrastructure and extensions. - Peter Flake; Frank Oppenheimer (FDL, 2013)

Verilog HDL and its ancestors and descendants. - Peter Flake; Phil Moorby; Steve Golson; Arturo Salz; Simon J. Davidmann (Proc. ACM Program. Lang., 2020)