Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE). - Stephen Roderick Hines; Yuval Peress; Peter Gavin; David B. Whalley; Gary S. Tyson (LCTES, 2009)

Improving data access efficiency by using a tagless access buffer (TAB). - Alen Bardizbanyan; Peter Gavin; David B. Whalley; Magnus Själander; Per Larsson-Edefors; Sally A. McKee; Per Stenström (CGO, 2013)

Improving processor efficiency by statically pipelining instructions. - Ian Finlayson; Brandon Davis; Peter Gavin; Gang-Ryung Uh; David B. Whalley; Magnus Själander; Gary S. Tyson (LCTES, 2013)

Reducing instruction fetch energy in multi-issue processors. - Peter Gavin; David B. Whalley; Magnus Själander (ACM Trans. Archit. Code Optim., 2013)

Scheduling instruction effects for a statically pipelined processor. - B. Davis; Ryan Baird; Peter Gavin; Magnus Själander; Ian Finlayson; F. Rasapour; G. Cook; Gang-Ryung Uh; David B. Whalley; Gary S. Tyson (CASES, 2015)

Optimizing Transfers of Control in the Static Pipeline Architecture. - Ryan Baird; Peter Gavin; Magnus Själander; David B. Whalley; Gang-Ryung Uh (LCTES, 2015)

Redesigning a tagless access buffer to require minimal ISA changes. - Carlos Sanchez; Peter Gavin; Daniel Moreau; Magnus Själander; David B. Whalley; Per Larsson-Edefors; Sally A. McKee (CASES, 2016)