A low jitter triple-band digital LC PLL in 130nm CMOS. - Nicola Da Dalt; Edwin Thaller; Peter Gregorius; Lajos Gazsi (ESSCIRC, 2004)

A compact triple-band low-jitter digital LC PLL with programmable coil in 130-nm CMOS. - Nicola Da Dalt; Edwin Thaller; Peter Gregorius; Lajos Gazsi (IEEE J. Solid State Circuits, 2005)

Cascading Techniques for a High-Speed Memory Interface. - Zheng Gu; Peter Gregorius; Daniel Kehrer; Lydia Neumann; Evelyn Neuscheler; Thomas Rickes; Hermann Ruckerbauer; Ralf Schledz; Martin Streibl; Jürgen Zielbauer (ISSCC, 2007)

75nm 7Gb/s/pin 1Gb GDDR5 graphics memory device with bandwidth-improvement techniques. - Rex Kho; David Boursin; Martin Brox; Peter Gregorius; Heinz Hoenigschmid; Bianka Kho; Sabine Kieser; Daniel Kehrer; Maksim Kuzmenka; Udo Moeller; Pavel Veselinov Petkov; Manfred Plan; et al. (ISSCC, 2009)

A 75 nm 7 Gb/s/pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques. - Rex Kho; David Boursin; Martin Brox; Peter Gregorius; Heinz Hoenigschmid; Bianka Kho; Sabine Kieser; Daniel Kehrer; Maksim Kuzmenka; Udo Moeller; Pavel Veselinov Petkov; Manfred Plan; et al. (IEEE J. Solid State Circuits, 2010)

Adaptive Equalizer Training for High-Speed Low-Power Communication Systems. - Yuan Fang; Ling Chen; Ashok Jaiswal; Klaus Hofmann; Peter Gregorius (DSD, 2013)

Adaptive Low-Power Synchronization Technique for Multiple Source-Synchronous Clocks in High-Speed Communication Systems. - Ashok Jaiswal; Yuan Fang; Peter Gregorius; Klaus Hofmann (DSD, 2013)

A 10 GbE TCP/IP hardware stack as part of a protocol acceleration platform. - Ulrich Langenbach; A. Berthe; Boris Traskov; S. Weide; Klaus Hofmann; Peter Gregorius (ICCE-Berlin, 2013)

Hardware architecture of an Internet Protocol Version 6 processor. - Boris Traskov; Ulrich Langenbach; Klaus Hofmann; Peter Gregorius (SoCC, 2014)