A prototype FPGA for subthreshold-optimized CMOS (abstract only). - Peter Grossmann; Miriam Leeser (FPGA, 2011)

Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA. - Peter Grossmann; Miriam Leeser; Marvin Onabajo (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

Minimum energy operation for clustered island-style FPGAs. - Peter Grossmann; Miriam Leeser; Marvin Onabajo (FPGA, 2013)

Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (CoRR, 2022)

Invited: Pre-silicon Side Channel and Fault Analysis. - Jasper Van Woudenberg; Peter Grossmann; Avinash Varna 001; Joseph Friel; Daniel Dinu; Ronnie Lindsay; Steve J. Brown (DAC, 2023)

Gate-Level Side-Channel Leakage Ranking With Architecture Correlation Analysis. - Pantea Kiaei; Yuan Yao; Zhenyuan Liu; Nicole Fern; Cees-Bart Breunesse; Jasper Van Woudenberg; Kate Gillis; Alex Dich; Peter Grossmann; Patrick Schaumont (IEEE Trans. Emerg. Top. Comput., 2024)