1.5 Gbit/s FPGA Implementation of a Fully-Parallel Turbo Decoder Designed for Mission-Critical Machine-Type Communication Applications. - An Li; Peter Hailes; Robert G. Maunder; Bashir M. Al-Hashimi; Lajos Hanzo (IEEE Access, 2016)

A Survey of FPGA-Based LDPC Decoders. - Peter Hailes; Lei Xu 005; Robert G. Maunder; Bashir M. Al-Hashimi; Lajos Hanzo (IEEE Commun. Surv. Tutorials, 2016)

A Flexible FPGA-Based Quasi-Cyclic LDPC Decoder. - Peter Hailes; Lei Xu 005; Robert G. Maunder; Bashir M. Al-Hashimi; Lajos Hanzo (IEEE Access, 2017)

Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations. - Peter Hailes; Lei Xu 005; Robert G. Maunder; Bashir M. Al-Hashimi; Lajos Hanzo (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations. - Shuai Shao; Peter Hailes; Tsang-Yi Wang; Jwo-Yuh Wu; Robert G. Maunder; Bashir M. Al-Hashimi; Lajos Hanzo (IEEE Commun. Surv. Tutorials, 2019)