Detailed routing architectures for embedded programmable logic IP cores. - Peter Hallschmid; Steven J. E. Wilton (FPGA, 2001)

Routing architecture optimizations for high-density embedded programmable IP cores. - Peter Hallschmid; Steven J. E. Wilton (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Fast Configuration of an Energy-Efficient Branch Predictor. - Peter Hallschmid; Resve A. Saleh (ISVLSI, 2006)

Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling. - Peter Hallschmid; Resve A. Saleh (DAC, 2007)

Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs. - Peter Hallschmid; Resve A. Saleh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks. - Rehan Ahmed; Peter Hallschmid (FPL, 2011)

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs. - Rehan Ahmed; Assem A. M. Bsoul; Steven J. E. Wilton; Peter Hallschmid; Richard Klukas (FPL, 2014)

Hierarchical Dynamic Power-Gating in FPGAs. - Rehan Ahmed; Steven J. E. Wilton; Peter Hallschmid; Richard Klukas (ARC, 2015)

Local congestion and blockage aware routability analysis using adaptive flexible modeling. - André Ivanov; Peter Hallschmid; Zhonghua Zhou (ICECS, 2016)