Boundary-scan design for cost-sensitive applications. - Peter Harrod (Microprocess. Microsystems, 1993)

Testing reusable IP-a case study. - Peter Harrod (ITC, 1999)

Test in the Emerging Intellectual Property Business. - Robin Saxby; Peter Harrod (IEEE Des. Test Comput., 1999)

Microprocessor cores. - Andrew Burdass; Gary Campbell; Richard Grisenthwaite; David Gwilt; Peter Harrod; Richard York (ETW, 2000)

The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data. - Michael G. Wahl; Sudipta Bhawmik; Kamran Zarrineh; Pradipta Ghosh; Scott Davidson 001; Peter Harrod (ITC, 2003)

Dynamic Voltage Scaling Aware Delay Fault Testing. - Noohul Basheer Zain Ali; Mark Zwolinski; Bashir M. Al-Hashimi; Peter Harrod (ETS, 2006)

Resistive Bridging Faults DFT with Adaptive Power Management Awareness. - Urban Ingelsson; Paul M. Rosinger; S. Saqib Khursheed; Bashir M. Al-Hashimi; Peter Harrod (ATS, 2007)

Variation Aware Analysis of Bridging Fault Testing. - Urban Ingelsson; Bashir M. Al-Hashimi; Peter Harrod (ATS, 2008)

Bridge Defect Diagnosis for Multiple-Voltage Design. - S. Saqib Khursheed; Paul M. Rosinger; Bashir M. Al-Hashimi; Sudhakar M. Reddy; Peter Harrod (ETS, 2008)

A New Approach for Transient Fault Injection Using Symbolic Simulation. - Ashish Darbari; Bashir M. Al-Hashimi; Peter Harrod; Daryl Bradley (IOLTS, 2008)

Bridging Fault Test Method With Adaptive Power Management Awareness. - S. Saqib Khursheed; Urban Ingelsson; Paul M. Rosinger; Bashir M. Al-Hashimi; Peter Harrod (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing. - S. Saqib Khursheed; Bashir M. Al-Hashimi; Peter Harrod (DATE, 2009)

Process Variation-Aware Test for Resistive Bridges. - Urban Ingelsson; Bashir M. Al-Hashimi; S. Saqib Khursheed; Sudhakar M. Reddy; Peter Harrod (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Diagnosis of Multiple-Voltage Design With Bridge Defect. - S. Saqib Khursheed; Bashir M. Al-Hashimi; Sudhakar M. Reddy; Peter Harrod (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Gate-Sizing-Based Single Vdd Test for Bridge Defects in Multivoltage Designs. - S. Saqib Khursheed; Bashir M. Al-Hashimi; Krishnendu Chakrabarty; Peter Harrod (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Current testing: Dead or alive? - Hans A. R. Manhaeve; Pete Harrod; Adit D. Singh; Chintan Patel; Ralf Arnolc; Davide Appello (ETS, 2013)

Error Correlation Prediction in Lockstep Processors for Safety-Critical Systems. - Emre Ozer 001; Balaji Venu; Xabier Iturbe; Shidhartha Das; Spyros Lyberis; John Biggs; Peter Harrod; John Penton (MICRO, 2018)

Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture. - Xabier Iturbe; Balaji Venu; Juergen Jagst; Emre Ozer 001; Peter Harrod; Chris Turner; John Penton (IEEE Des. Test, 2018)

An Exploration of Microprocessor Self-Test Optimisation Based On Safe Faults. - Anuraag Narang; Balaji Venn; S. Saqib Khursheed; Peter Harrod (DFT, 2021)

Memories From IBM 370 to ARM. - Pete Harrod (IEEE Micro, 2021)