H. Peter Hofstee

According to our database, H. Peter Hofstee authored at least 83 papers between 1990 and 2023.

Collaborative distances:

• Dijkstra number of two.
• Erdős number of three.

2023

An Intermediate Representation for Composable Typed Streaming Dataflow Designs.

Matthijs A. Reukers, Yongding Tian, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten

Proceedings of the Joint Proceedings of Workshops at the 49th International Conference on Very Large Data Bases (VLDB 2023), Vancouver, Canada, August 28, 2023

Tydi-lang: A Language for Typed Streaming Hardware.

Yongding Tian, Matthijs A. Reukers, Zaid Al-Ars, H. Peter Hofstee, Matthijs Brobbel, Johan Peltenburg, Jeroen van Straten

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications.

Zaid Al-Ars, Jakoba Petri-Koenig, Joost Hoozemans, Luc Dierick, H. Peter Hofstee

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Tydi-Chisel: Collaborative and Interface-Driven Data-Streaming Accelerators.

Casper Cromjongh, Yongding Tian, H. Peter Hofstee, Zaid Al-Ars

Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023

2022

The Future of FPGA Acceleration in Datacenters and the Cloud.

Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, H. Peter Hofstee, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier

ACM Trans. Reconfigurable Technol. Syst., 2022

A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics: Defining an IR for Composable Typed Streaming Dataflow Designs.

Matthijs A. Reukers, H. Peter Hofstee, Zaid Al-Ars

CoRR, 2022

Tydi-lang: a language for typed streaming hardware - A manual for future Tydi-lang compiler developers.

Yongding Tian, Zaid Al-Ars, H. Peter Hofstee

CoRR, 2022

Benchmarking Apache Arrow Flight - A wire-speed protocol for data transfer, querying and microservices.

Tanveer Ahmad, Zaid Al-Ars, H. Peter Hofstee

CoRR, 2022

Communication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight.

Tanveer Ahmad, Chengxin Ma, Zaid Al-Ars, H. Peter Hofstee

Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022

SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs.

Seongyeon Park, Hajin Kim, Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee, Youngsok Kim, Jinho Lee

Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

Improving Gradient Paths for Binary Convolutional Neural Networks.

Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars

Proceedings of the 33rd British Machine Vision Conference 2022, 2022

2021

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow.

Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee

J. Signal Process. Syst., 2021

Low Latency and High Throughput Write-Ahead Logging Using CAPI-Flash.

Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee

IEEE Trans. Cloud Comput., 2021

AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression.

Baozhou Zhu, H. Peter Hofstee, Johan Peltenburg, Jinho Lee, Zaid Al-Ars

Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021

An Attention Module for Convolutional Neural Networks.

Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars

Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021

2020

An Efficient High-Throughput LZ77-Based Decompressor in Reconfigurable Logic.

Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee

J. Signal Process. Syst., 2020

In-memory database acceleration on FPGAs: a survey.

Jian Fang, Yvo T. B. Mulder, Jan Hidders, Jinho Lee, H. Peter Hofstee

VLDB J., 2020

Tydi: An Open Specification for Complex Data Structures Over Hardware Streams.

Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee

IEEE Micro, 2020

SoFAr: Shortcut-based Fractal Architectures for Binary Convolutional Neural Networks.

Baozhou Zhu, H. Peter Hofstee, Jinho Lee, Zaid Al-Ars

CoRR, 2020

Optimizing performance of GATK workflows using Apache Arrow In-Memory data framework.

Tanveer Ahmad, Nauman Ahmed, Zaid Al-Ars, H. Peter Hofstee

BMC Genom., 2020

REAF: Reducing Approximation of Channels by Reducing Feature Reuse Within Convolution.

Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee

IEEE Access, 2020

ThymesisFlow: A Software-Defined, HW/SW co-Designed Interconnect Stack for Rack-Scale Memory Disaggregation.

Christian Pinto, Dimitris Syrivelis, Michele Gazzetti, Panos K. Koutsovasilis, Andrea Reale, Kostas Katrinis, H. Peter Hofstee

Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

NASB: Neural Architecture Search for Binary Convolutional Neural Networks.

Baozhou Zhu, Zaid Al-Ars, H. Peter Hofstee

Proceedings of the 2020 International Joint Conference on Neural Networks, 2020

Battling the CPU Bottleneck in Apache Parquet to Arrow Conversion Using FPGA.

Johan Peltenburg, Lars T. J. van Leeuwen, Joost Hoozemans, Jian Fang, Zaid Al-Ars, H. Peter Hofstee

Proceedings of the International Conference on Field-Programmable Technology, 2020

2019

Video-Text Compliance: Activity Verification Based on Natural Language Instructions.

Mayoore Jaiswal, H. Peter Hofstee, Valerie Chen, Suvadip Paul, Rogério Feris, Frank Liu, Anupama Jagannathan, Anne Gattiker, Inseok Hwang, Jinho Lee, Matthew Tong, Sahil Dureja, Soham Shah

Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision Workshops, 2019

Fletcher: A Framework to Efficiently Integrate FPGA Accelerators with Apache Arrow.

Johan Peltenburg, Jeroen van Straten, Lars Wijtemans, Lars van Leeuwen, Zaid Al-Ars, H. Peter Hofstee

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model.

Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Refine and Recycle: A Method to Increase Decompression Parallelism.

Jian Fang, Jianyu Chen, Jinho Lee, Zaid Al-Ars, H. Peter Hofstee

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow.

Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, H. Peter Hofstee, Zaid Al-Ars

Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019

2018

A hardware compilation framework for text analytics queries.

Raphael Polig, Kubilay Atasu, Heiner Giefers, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee

J. Parallel Distributed Comput., 2018

A 64-GB Sort at 28 GB/s on a 4-GPU POWER9 Node for Uniformly-Distributed 16-Byte Records with 8-Byte Keys.

Gordon C. Fossum, Ting Wang, H. Peter Hofstee

Proceedings of the High Performance Computing, 2018

A high-bandwidth snappy decompressor in reconfigurable logic: work-in-progress.

Jian Fang, Jianyu Chen, Zaid Al-Ars, H. Peter Hofstee, Jan Hidders

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018

CAPI-Flash Accelerated Persistent Read Cache for Apache Cassandra.

Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee

Proceedings of the 11th IEEE International Conference on Cloud Computing, 2018

2017

ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator.

Jinho Lee, Heesu Kim, Sungjoo Yoo, Kiyoung Choi, H. Peter Hofstee, Gi-Joon Nam, Mark Nutter, Damir A. Jamsek

Proc. VLDB Endow., 2017

Analyzing In-Memory Hash Join: Granularity Matters.

Jian Fang, Jinho Lee, H. Peter Hofstee, Jan Hidders

Proceedings of the International Workshop on Accelerating Analytics and Data Management Systems Using Modern Processor and Storage Architectures, 2017

SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale.

Hamid Mushtaq, Frank Liu, Carlos Costa, Gang Liu, H. Peter Hofstee, Zaid Al-Ars

Proceedings of the 8th ACM International Conference on Bioinformatics, 2017

2016

PATer: A Hardware Prefetching Automatic Tuner on IBM POWER8 Processor.

Minghua Li, Guancheng Chen, Qijun Wang, Yonghua Lin, H. Peter Hofstee, Per Stenström, Dian Zhou

IEEE Comput. Archit. Lett., 2016

RAW 2016 Keynotes.

H. Peter Hofstee, Patrick Lysaght, Dirk van den Heuvel

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Auto-tuning Spark Big Data Workloads on POWER8: Prediction-Based Dynamic SMT Threading.

Zhen Jia, Chao Xue, Guancheng Chen, Jianfeng Zhan, Lixin Zhang, Yonghua Lin, H. Peter Hofstee

Proceedings of the 2016 International Conference on Parallel Architectures and Compilation, 2016

Optimized Durable Commitlog for Apache Cassandra Using CAPI-Flash.

Bedri Sendir, Madhusudhan Govindaraju, Rei Odaira, H. Peter Hofstee

Proceedings of the 9th IEEE International Conference on Cloud Computing, 2016

2015

Feature detection for image analytics via FPGA acceleration.

Hua-Yu Chang, Iris Hui-Ru Jiang, H. Peter Hofstee, Damir A. Jamsek, Gi-Joon Nam

IBM J. Res. Dev., 2015

Second-Generation Big Data Systems.

Fadi H. Gebara, H. Peter Hofstee, Kevin J. Nowka

Computer, 2015

2014

Giving Text Analytics a Boost.

Raphael Polig, Kubilay Atasu, Laura Chiticariu, Christoph Hagleitner, H. Peter Hofstee, Frederick R. Reiss, Huaiyu Zhu, Eva Sitaridi

IEEE Micro, 2014

Hardware-accelerated text analytics.

Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Laura Chiticariu, Frederick Reiss, Huaiyu Zhu, H. Peter Hofstee

Proceedings of the 2014 IEEE Hot Chips 26 Symposium (HCS), 2014

2013

True hardware random number generation implemented in the 32-nm SOI POWER7+ processor.

John S. Liberty, Adrian Barrera, David W. Boerstler, Thomas B. Chadwick, Scott R. Cottier, H. Peter Hofstee, Julie A. Rosser, Marty L. Tsai

IBM J. Res. Dev., 2013

Understanding system design for Big Data workloads.

H. Peter Hofstee, Guan-Cheng Chen, Fadi H. Gebara, Kevin Hall, Jay Herring, Damir A. Jamsek, Jian Li, Yan Li, Juwei Shi, Peter Wai Yee Wong

IBM J. Res. Dev., 2013

Big Data text-oriented benchmark creation for Hadoop.

Anne E. Gattiker, Fadi H. Gebara, H. Peter Hofstee, J. D. Hayes, A. Hylick

IBM J. Res. Dev., 2013

2011

Cell Broadband Engine Processor.

H. Peter Hofstee

Proceedings of the Encyclopedia of Parallel Computing, 2011

2009

Heterogeneous Multi-core Processors: The Cell Broadband Engine.

H. Peter Hofstee

Proceedings of the Multicore Processors and Systems, 2009

The Next 25 Years of Computer Architecture?

H. Peter Hofstee

Proceedings of the Euro-Par 2009, 2009

HPPC 2009 Panel: Are Many-Core Computer Vendors on Track?

Martti Forsell, H. Peter Hofstee, Ahmed Jerraya, Chris R. Jesshope, Uzi Vishkin, Jesper Larsson Träff

Proceedings of the Euro-Par 2009, 2009

2008

Rome Reborn.

Bernard D. Frischer, Dean Abernathy, Gabriele Guidi, Joel Myers, Cassie Thibodeau, Antonio Salvemini, Pascal Müller, H. Peter Hofstee, Barry Minor

Proceedings of the International Conference on Computer Graphics and Interactive Techniques, 2008

2007

Cell Broadband Engine processor vault security architecture.

Kanna Shimizu, H. Peter Hofstee, John S. Liberty

IBM J. Res. Dev., 2007

Preface.

H. Peter Hofstee, Ashwini K. Nanda, John J. Ritsko

IBM J. Res. Dev., 2007

Microarchitecture and implementation of the synergistic processor in 65-nm and 90-nm SOI.

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia M. Müller, Osamu Takahashi, Koji Hirairi, Atsushi Kawasumi, Hiroaki Murakami, Hiromi Noro, Shoji Onishi, Juergen Pille, Joel Silberman, Suksoon Yong, Akiyuki Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, VanDung To, Eiji Iwata

IBM J. Res. Dev., 2007

The future of multi-core technologies.

Michael T. Clark, H. Peter Hofstee, Edward J. Barragy, Ian Buck, Stephen W. Keckler

Proceedings of the 2007 IEEE International Conference on Cluster Computing, 2007

Cell Broadband Engine Processor Design Methodology.

Osamu Takahashi, Erwin Behnen, Scott R. Cottier, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, C. J. Johnson, Stephen D. Posluszny

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Synergistic Processing in Cell's Multicore Architecture.

Michael Gschwind, H. Peter Hofstee, Brian K. Flachs, Martin Hopkins, Yukio Watanabe, Takeshi Yamazaki

IEEE Micro, 2006

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor.

Dac C. Pham, Tony Aipperspach, David Boerstler, Mark Bolliger, Rajat Chaudhry, Dennis Cox, Paul E. Harvey, H. Peter Hofstee, Charles R. Johns, Jim Kahle, Atsushi Kameyama, John M. Keaty, Yoshio Masubuchi, Mydung Pham, Jürgen Pille, Stephen D. Posluszny, Mack W. Riley, Daniel L. Stasiak, Masakazu Suzuoki, Osamu Takahashi, James D. Warnock, Stephen Weitzel, Dieter F. Wendel, Kazuaki Yazawa

IEEE J. Solid State Circuits, 2006

The microarchitecture of the synergistic processor for a cell processor.

Brian K. Flachs, Shigehiro Asano, Sang H. Dhong, H. Peter Hofstee, Gilles Gervais, Roy Kim, Tien Le, Peichun Liu, Jens Leenstra, John S. Liberty, Brad W. Michael, Hwa-Joon Oh, Silvia Melitta Müller, Osamu Takahashi, A. Hatakeyama, Yukio Watanabe, Naoka Yano, Daniel A. Brokenshire, Mohammad Peyravian, Vandung To, Eiji Iwata

IEEE J. Solid State Circuits, 2006

Invited speakers II - Real-time supercomputing and technology for games and entertainment.

H. Peter Hofstee

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Key features of the design methodology enabling a multi-core SoC implementation of a first-generation CELL processor.

Dac C. Pham, Hans-Werner Anderson, Erwin Behnen, Mark Bolliger, Sanjay Gupta, H. Peter Hofstee, Paul E. Harvey, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Sang Lee, Tuyen V. Nguyen, John G. Petrovick, Mydung Pham, Juergen Pille, Stephen D. Posluszny, Mack W. Riley, Joseph Verock, James D. Warnock, Steve Weitzel, Dieter F. Wendel

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

Introduction to the Cell multiprocessor.

James A. Kahle, Michael N. Day, H. Peter Hofstee, Charles R. Johns, Theodore R. Maeurer, David J. Shippy

IBM J. Res. Dev., 2005

Communication and Synchronization in the Cell Processor - Invited Talk.

H. Peter Hofstee

Proceedings of the 28th Communicating Process Architectures Conference, 2005

Power Efficient Processor Architecture and The Cell Processor.

H. Peter Hofstee

Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

Hardware and software architectures for the CELL processor.

H. Peter Hofstee, Michael N. Day

Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

The design methodology and implementation of a first-generation CELL processor: a multi-core SoC.

Dac C. Pham, Erwin Behnen, Mark Bolliger, H. Peter Hofstee, Charles R. Johns, James A. Kahle, Atsushi Kameyama, John M. Keaty, Bob Le, Yoshio Masubuchi, Stephen D. Posluszny, Mack W. Riley, Masakazu Suzuoki, Michael Wang, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Kazuaki Yazawa

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2002

Power-Constrained Microprocessor Design.

H. Peter Hofstee

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

2001

Timed circuit verification using TEL structures.

Wendy Belluomini, Chris J. Myers, H. Peter Hofstee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Derivation of a rotator circuit with homogeneous interconnect.

H. Peter Hofstee, Jun Sawada

Inf. Process. Lett., 2001

2000

Custom circuit design as a driver of microprocessor performance.

David H. Allen, Sang H. Dhong, H. Peter Hofstee, Jens Leenstra, Kevin J. Nowka, Daniel L. Stasiak, Dieter F. Wendel

IBM J. Res. Dev., 2000

"Timing closure by design, " a high frequency microprocessor design methodology.

Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Paula K. Coulman, Sang H. Dhong, Brian K. Flachs, H. Peter Hofstee, Nobuo Kojima, Ohsang Kwon, Kyung T. Lee, David Meltzer, Kevin J. Nowka, J. Park, J. Peter, Joel Silberman, Osamu Takahashi, Paul Villarrubia

Proceedings of the 37th Conference on Design Automation, 2000

1999

Beyond 1 GHz.

H. Peter Hofstee, Kevin J. Nowka

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

Verification of Delayed-Reset Domino Circuits Using ATACS.

Wendy Belluomini, Chris J. Myers, H. Peter Hofstee

Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1998

Designing for a gigahertz [guTS integer processor].

H. Peter Hofstee, Sang H. Dhong, David Meltzer, Kevin J. Nowka, Joel Silberman, Jeffrey L. Burns, Stephen D. Posluszny, Osamu Takahashi

IEEE Micro, 1998

A 1.0-GHz single-issue 64-bit powerPC integer processor.

Joel Silberman, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Axel Essbaum, Uttam Ghoshal, David F. Heidel, H. Peter Hofstee, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Stephen D. Posluszny, Osamu Takahashi, Ivan Vo, Brian A. Zoric

IEEE J. Solid State Circuits, 1998

High-Speed Serializing/De-Serializing Design-For-Test Method for Evaluating a 1 GHz Microprocessor.

David F. Heidel, Sang H. Dhong, H. Peter Hofstee, Michael Immediato, Kevin J. Nowka, Joel Silberman, Kevin Stawiasz

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

A 690 ps read-access latency register file for a GHz integer microprocessor.

Osamu Takahashi, Joel Silberman, Sang H. Dhong, H. Peter Hofstee, Naoaki Aoki

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Design methodology for a 1.0 GHz microprocessor.

Stephen D. Posluszny, Naoaki Aoki, David Boerstler, Jeffrey L. Burns, Sang H. Dhong, Uttam Ghoshal, H. Peter Hofstee, David P. LaPotin, Kyung T. Lee, David Meltzer, Hung C. Ngo, Kevin J. Nowka, Joel Silberman, Osamu Takahashi, Ivan Vo

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

1997

Circuits and Microarchitecture for Gigahertz VLSI Designs.

Kevin J. Nowka, H. Peter Hofstee

Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997

1994

Distributing a Class of Sequential Programs.

H. Peter Hofstee

Sci. Comput. Program., 1994

1991

A Distributed Implementation of a Task Pool.

H. Peter Hofstee, Johan J. Lukkien, Jan L. A. van de Snepscheut

Proceedings of the Research Directions in High-Level Parallel Programming Languages, 1991

1990

Distributed Sorting.

H. Peter Hofstee, Alain J. Martin, Jan L. A. van de Snepscheut

Sci. Comput. Program., 1990