Circuit design techniques for the high-performance CMOS IBM S/390 Parallel Enterprise Server G4 microprocessor. - Leon J. Sigal; James D. Warnock; Brian W. Curran; Yuen H. Chan; Peter J. Camporese; Mark D. Mayo; William V. Huott; Daniel R. Knebel; Ching-Te Chuang; James P. Eckhardt; Philip T. Wu (IBM J. Res. Dev., 1997)

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. - Charles F. Webb; Carl J. Anderson; Leon J. Sigal; Kenneth L. Shepard; John S. Liptay; James D. Warnock; Brian W. Curran; Barry Krumm; Mark D. Mayo; Peter J. Camporese; Eric M. Schwarz; Mark S. Farrell; et al. (IEEE J. Solid State Circuits, 1997)

Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors. - Robert M. Averill III; Keith G. Barkley; Michael A. Bowen; Peter J. Camporese; Allan H. Dansky; Robert F. Hatch; Dale E. Hoffman; Mark D. Mayo; Scott A. McCabe; Timothy G. McNamara; Thomas J. McPherson; Gregory A. Northrop; et al. (IBM J. Res. Dev., 1999)

A clock distribution network for microprocessors. - Phillip J. Restle; Timothy G. McNamara; David A. Webber; Peter J. Camporese; Kwok F. Eng; Keith A. Jenkins; David H. Allen; Michael J. Rohn; Michael P. Quaranta; David W. Boerstler; Charles J. Alpert; Craig A. Carter; et al. (IEEE J. Solid State Circuits, 2001)

IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology. - Brian W. Curran; Yuen H. Chan; Philip T. Wu; Peter J. Camporese; Gregory A. Northrop; Robert F. Hatch; Lisa B. Lacey; James P. Eckhardt; David T. Hui; Howard H. Smith (IBM J. Res. Dev., 2002)

IBM POWER6 microprocessor physical design and design methodology. - Rex Berridge; Robert M. Averill III; Arnold E. Barish; Michael A. Bowen; Peter J. Camporese; Jack DiLullo; Peter E. Dudley; Joachim Keinert; David W. Lewis; Robert D. Morel; Thomas E. Rosser; Nicole S. Schwartz; et al. (IBM J. Res. Dev., 2007)