Peter Koch

According to our database1, Peter Koch authored at least 20 papers between 1986 and 2016.

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Bibliography

2016
Energy-aware scheduling of FIR filter structures using a timed automata model.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
On the Blind Recovery of Cardiac and Respiratory Sounds.
IEEE J. Biomedical and Health Informatics, 2015

Architectural design space exploration of an FPGA-based compressed sampling engine: Application to wireless heart-rate monitoring.
Proceedings of the Nordic Circuits and Systems Conference, 2015

2014
Vertraulichkeit für den Auskunftsdienst im Internet?
Datenschutz und Datensicherheit, 2014

Analysis of Acoustic Cardiac Signals for Heart Rate Variability and Murmur Detection Using Nonnegative Matrix Factorization-Based Hierarchical Decomposition.
Proceedings of the 2014 IEEE International Conference on Bioinformatics and Bioengineering, 2014

2013
Empirical verification of fault models for FPGAs operating in the subcritical voltage region.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

2011
Time and Power optimizations in FPGA-based architectures for polyphase channelizers.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
SystemC-AMS SDF model synthesis for exploration of heterogeneous architectures.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Combined matched filter and arbitrary interpolator for symbol timing synchronization in SDR receivers.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009
DS-CDMA Descrambling and Despreading with the Cell Broadband Engine.
Proceedings of the 2009 International Conference on Signal Acquisition and Processing, 2009

Scheduling Temporal Partitions in a Multiprocessing Paradigm for Reconfigurable Architectures.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009

2008
A Priori Implementation Effort Estimation for Hardware Design Based on Independent Path Analysis.
EURASIP J. Emb. Sys., 2008

2007
Automated distributed simulation in PTOLEMY II.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2007

2004
On Combined DVS and Processor Evaluation.
Proceedings of the Integrated Circuit and System Design, 2004

2003
AsmL Specification of a Ptolemy II Scheduler.
Proceedings of the Abstract State Machines, 2003

1999
A Project-oriented Master Programme in "DSP Algorithms and ASIC Architectures".
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

1995
Simulated Annealing Applied to Compile Time Scheduling onto Multiple DSP Architectures.
Proceedings of the Seventh IASTED/ISMM International Conference on Parallel and Distributed Computing and Systems, 1995

Static Scheduling of Data Independent Scientific Computations onto Multi-DSP Architectures using Simulated Annealing.
Proceedings of the Parallel Computing: State-of-the-Art and Perspectives, 1995

1993
An ecological man-machine interface for temporal visualization.
Proceedings of the 1st International Workshop on Intelligent User Interfaces, 1993

1986
Some Problems of Building Process Control Expert Systems.
Proceedings of the Intelligent Autonomous Systems, 1986


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