Reduction of Latency and Resource Usage in Bit-Level Pipelined Data Paths for FPGAs. - Peter Kollig; Bashir M. Al-Hashimi (FPGA, 1999)

Impact of multicycled scheduling on power-area tradeoffs in behavioural synthesis. - M. A. Ochoa-Montiel; Bashir M. Al-Hashimi; Peter Kollig (ISCAS (4), 2005)

Exploiting Power-Area Tradeoffs in Behavioural Synthesis through clock and operations throughput selection. - M. A. Ochoa-Montiel; Bashir M. Al-Hashimi; Peter Kollig (ASP-DAC, 2007)

Heterogeneous multi-core platform for consumer multimedia applications. - Peter Kollig; Colin Osborne; Tomas Henriksson (DATE, 2009)

Design of a low power MPEG-1 motion vector reconstructor. - M. A. Ochoa-Montiel; Bashir M. Al-Hashimi; Peter Kollig (SBCCI, 2009)