A 60Gb/s PAM-4 ADC-DSP Transceiver in 7nm CMOS with SNR-Based Adaptive Power Scaling Achieving 6.9pJ/b at 32dB Loss. - Marc-Andre LaCroix; Henry Wong; Yun Hua Liu; Huong Ho; Semyon Lebedev; Petar Krotnev; Dorin Alexandru Nicolescu; Dmitry Petrov; Carlos Carvalho; Stephen Alie; Euhan Chong; Faisal Ahmed Musa; et al. (ISSCC, 2019)

Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation. - Ming Yang 005; Shayan Shahramian; Hossein Shakiba; Henry Wong; Peter Krotnev; Anthony Chan Carusone (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET. - Euhan Chong; Faisal Ahmed Musa; Ahmed N. Mustafa; Tim Gao; Peter Krotnev; Rashid Soreefan; Qian Xin; Paul Madeira; Davide Tonietto (ESSCIRC, 2021)

Pre-FEC and Post-FEC BER as Criteria for Optimizing Wireline Transceivers. - Ming Yang 005; Shayan Shahramian; Henry Wong; Peter Krotnev; Anthony Chan Carusone (ISCAS, 2021)

A 112Gb/s PAM-4 Low-Power 9-Tap Sliding-Block DFE in a 7nm FinFET Wireline Receiver. - James Bailey 002; Hossein Shakiba; Ehud Nir; Grigory Marderfeld; Peter Krotnev; Marc-Andre LaCroix; David Cassan (ISSCC, 2021)

8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2. - Marc-Andre LaCroix; Euhan Chong; Weilun Shen; Ehud Nir; Faisal Ahmed Musa; Haitao Mei 002; Mohammad-Mahdi Mohsenpour; Semyon Lebedev; Babak Zamanlooy; Carlos Carvalho; Qian Xin; Dmitry Petrov; et al. (ISSCC, 2021)

A 112-Gb/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver. - James Bailey 002; Hossein Shakiba; Ehud Nir; Grigory Marderfeld; Peter Krotnev; Marc-Andre LaCroix; David Cassan; Davide Tonietto (IEEE J. Solid State Circuits, 2022)