Special-purpose parallel architectures for high-performance machine learning. - Roberto Battiti; Peter Lee 002; Alvise Sartori; Giampietro Tecchiolli (HPCN Europe, 1995)

An FPFA Based Object Recognition Machine. - Ali Zakerolhosseini; Peter Lee 002; Ed Horne (FPL, 1998)

Combined Geometric Transformation and Illumination Invariant Object Recognition in RGB Color Images. - Stavros Paschalakis; Peter Lee 002 (ICPR, 2000)

Statistical Pattern Recognition Using the Normalized Complex Moment Components Vector. - Stavros Paschalakis; Peter Lee 002 (SSPR/SPR, 2000)

SoftTOTEM: An FPGA Implementation of the TOTEM Parallel Processor. - Stephanie McBader; Luca Clementel; Alvise Sartori; Andrea Boni; Peter Lee 002 (FPL, 2002)

A programmable image signal processing architecture for embedded vision systems. - Stephanie McBader; Peter Lee 002 (DSP, 2002)

An FPGA System for the High Speed Extraction, Normalization and Classification of Moment Descriptors. - Stavros Paschalakis; Peter Lee 002; Miroslaw Bober (FPL, 2003)

Double precision floating-point arithmetic on FPGAs. - Stavros Paschalakis; Peter Lee 002 (FPT, 2003)

An FPGA Implementation of a Flexible, Parallel Image Processing Architecture Suitable for Embedded Vision Systems. - Stephanie McBader; Peter Lee 002 (IPDPS, 2003)

The impact of modern FPGA architectures on neural hardware: a case study of the TOTEM neural processor. - Stephanie McBader; Peter Lee 002; Alvise Sartori (IJCNN, 2004)

Least squares adaptive algorithms suitable for multiplierless LMMSE detection in 3rd generation mobile systems. - Charan Litchfield; Richard J. Langley; Peter Lee 002; John C. Batchelor (PIMRC, 2005)

The use of hybrid logarithmic arithmetic for root raised cosine matched filters in WCDMA downlink receivers. - Charan Litchfield; Richard J. Langley; Peter Lee 002; John C. Batchelor (WCNC, 2005)

On-line Nonintrusive Measurement of Particle Size Distribution Through Digital Imaging. - Robert M. Carter; Yong Yan 001; Peter Lee 002 (IEEE Trans. Instrum. Meas., 2006)

Mass Flow Measurement of Fine Particles in a Pneumatic Suspension Using Electrostatic Sensing and Neural Network Techniques. - Yong Yan 001; Lijun Xu 001; Peter Lee 002 (IEEE Trans. Instrum. Meas., 2006)

Cellular Automata Based Binary Arithmetic for use on Self Repairing, Fault Tolerant Hardware. - James Lloyd Weston; Peter Lee 002 (AHS, 2007)

An Efficient Implementation of a 2D DWT on FPGA. - Michael Wisdom; Peter Lee 002 (FPL, 2007)

Evaluation of a Hybrid-Log 2D Wavelet Image Transform. - Michael Wisdom; Peter Lee 002 (DSP, 2007)

An Unbounded Parallel Binary Tree Adder for use on a Cellular Platform. - James Lloyd Weston; Peter Lee 002 (ALIFE, 2007)

LogTOTEM: A Logarithmic Neural Processor and its Implementation on an FPGA Fabric. - Peter Lee 002; Esther Costa; Stephanie McBader; Luca Clementel; Alvise Sartori (IJCNN, 2007)

Logarithmic Codecs for Adaptive Beamforming in WCDMA Downlink Channels. - Charan Litchfield; Peter Lee 002; Richard J. Langley; John C. Batchelor (ISCAS, 2007)

FPGA Implementation of Cellular Automata Spaces Using a CAM Based Cellular Architecture. - James Lloyd Weston; Peter Lee 002 (AHS, 2008)

Analysis of Time and Frequency Domain Performance of MFIR Filters. - Jean-Jacques Vandenbussche; Peter Lee 002; Joan Peuteman (ESA, 2008)

An implementation of a multiplierless Hough transform on an FPGA platform using hybrid-log arithmetic. - Peter Lee 002; Evangelos Alexiadis (Real-Time Image Processing, 2008)

Hybrid-logarithmic arithmetic and applications. - Peter Lee 002 (2011)

On the coefficient quantization of Multiplicative FIR filters. - Jean-Jacques Vandenbussche; Peter Lee 002; Joan Peuteman (Digit. Signal Process., 2013)

Two-stage logarithmic converter with reduced memory requirements. - Mandeep Chaudhary; Peter Lee 002 (IET Comput. Digit. Tech., 2014)

On the Accuracy of Digital Phase Sensitive Detectors Implemented in FPGA Technology. - Jean-Jacques Vandenbussche; Peter Lee 002; Joan Peuteman (IEEE Trans. Instrum. Meas., 2014)

Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays. - Jean-Jacques Vandenbussche; Peter Lee 002; Joan Peuteman (IET Signal Process., 2015)

An Improved Two-Step Binary Logarithmic Converter for FPGAs. - Mandeep Chaudhary; Peter Lee 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)