Two Fault Injection Techniques for Test of Fault Handling Mechanisms. - Johan Karlsson; Ulf Gunneflo; Peter Lidén; Jan Torin (ITC, 1991)

Transistor Fault Coverage for Self-Testing CMOS Checkers. - Peter Lidén; Peter Dahlgren; Jan Torin (ITC, 1992)

Efficient modeling of switch-level networks containing undetermined logic node states. - Peter Dahlgren; Peter Lidén (ICCAD, 1993)

Modeling of Intermediate Node States in switch-Level Networks. - Peter Dahlgren; Peter Lidén (DAC, 1994)

On Latching Probability of Particle Induced Transients in Combinational Networks. - Peter Lidén; Peter Dahlgren; Rolf Johansson 002; Johan Karlsson (FTCS, 1994)

Using heavy-ion radiation to validate fault-handling mechanisms. - Johan Karlsson; Peter Lidén; Peter Dahlgren; Rolf Johansson 002; Ulf Gunneflo (IEEE Micro, 1994)

A Switch-level Algorithm for Simulation of Transients in Combinational Logic. - Peter Dahlgren; Peter Lidén (FTCS, 1995)

Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers. - Peter Lidén; Peter Dahlgren (ISCAS, 1995)

Switch-level modeling of transistor-level stuck-at faults. - Peter Lidén; Peter Dahlgren (VTS, 1995)

Fault Simulation and Physical Fault Injection Applied to MOS Transistor Networks. - Peter Lidén (1995)

A fault model for switch-level simulation of gate-to-drain shorts. - Peter Dahlgren; Peter Lidén (VTS, 1996)