The Use of Combinators in Translating A Purely Functional Language to Low-Level Data-Flow Graphs. - Peter M. Maurer; Arthur E. Oldehoeft (Comput. Lang., 1983)

Mapping the Data Flow Model of Computation into an Enhanced Von Neumann Processor. - Peter M. Maurer (ICPP (1), 1988)

Design verification of the WE 32106 math accelerator unit. - Peter M. Maurer (IEEE Des. Test, 1988)

A logic-to-logic comparator for VLSI layout verification. - Peter M. Maurer; Alexander D. Schapira (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988)

Scheduling High-Level Blocks for Functional Simulation. - Zhicheng Wang; Peter M. Maurer (DAC, 1989)

The FHDL macro processor. - Peter M. Maurer (ACM Southeast Regional Conference, 1990)

The FHDL PLA tools. - Peter M. Maurer; Craig D. Morency (ACM Southeast Regional Conference, 1990)

The FHDL ROM tools. - Peter M. Maurer; Craig D. Morency (ACM Southeast Regional Conference, 1990)

Techniques for Unit-Delay Compiled Simulation. - Peter M. Maurer; Zhicheng Wang (DAC, 1990)

LECSIM: A Levelized Event Driven Compiled Logic Simulation. - Zhicheng Wang; Peter M. Maurer (DAC, 1990)

Optimization of the Parallel Technique for Compiled Unit-Delay Simulation. - Peter M. Maurer (ICCAD, 1990)

Dynamic Functional Testing for VLSI Circuits. - Peter M. Maurer (IEEE Des. Test Comput., 1990)

Generating Test Data with Enhanced Context-Free Grammars. - Peter M. Maurer (IEEE Softw., 1990)

Scheduling blocks of hierarchical compiled simulation of combinational circuits. - Peter M. Maurer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Two New Techniques for Compiled Multi-Delay Logic Simulation. - Yun Sik Lee; Peter M. Maurer (DAC, 1992)

The Design and Implementation of a Grammar-based Data Generator. - Peter M. Maurer (Softw. Pract. Exp., 1992)

Two new techniques for unit-delay compiled simulation. - Peter M. Maurer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

Parallel multi-delay simulation. - Yun Sik Lee; Peter M. Maurer (ICCAD, 1993)

The shadow algorithm: a scheduling technique for both compiled and interpreted simulation. - Peter M. Maurer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993)

Gateways: a technique for adding event-driven behavior to compiled simulations. - Peter M. Maurer; Yun Sik Lee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994)

Unit delay simulation with the inversion algorithm. - William J. Schilp; Peter M. Maurer (ICCAD, 1996)

Is Compiled Simulation Really Faster than Interpreted Simulation? - Peter M. Maurer (VLSI Design, 1996)

Bit-parallel multidelay simulation. - Yun Sik Lee; Peter M. Maurer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

The inversion algorithm for digital simulation. - Peter M. Maurer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Software Bit-Slicing: A Technique for Improving Simulation Performance. - Peter M. Maurer; William J. Schilp (DATE, 1999)

Efficient Simulation for Hierarchical and Partitioned Circuits. - Peter M. Maurer (VLSI Design, 1999)

Logic Simulation Using Networks of State Machines. - Peter M. Maurer (DATE, 2000)

Event Driven Simulation Without Loops or Conditionals. - Peter M. Maurer (ICCAD, 2000)

State-Machine Based Logic Simulation Using Three Logic Values. - Peter M. Maurer; William J. Schilp (VLSI Design, 2000)

Components: What If They Gave a Revolution and Nobody Came? - Peter M. Maurer (Computer, 2000)

Identifying an appropriate view of software components for undergraduate education. - Allen S. Parrish; Joe Hollingsworth; Peter M. Maurer; Benjamin Shults; Bruce W. Weide (SIGCSE, 2001)

Random Characterization of Design Automation Algorithms. - Sandeep K. Kondapuram; Peter M. Maurer (ISVLSI, 2003)

Efficient event-driven simulation by exploiting the output observability of gate clusters. - Peter M. Maurer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Metamorphic Programming: Unconventional High Performance. - Peter M. Maurer (Computer, 2004)

How to Make Program Assessment Work for You. - William B. Poucher; Peter M. Maurer (FECS, 2005)

Converting command-line applications into binary components. - Peter M. Maurer (Softw. Pract. Exp., 2005)

Using conjugate symmetries to enhance gate-level simulations. - Peter M. Maurer (DATE, 2006)

Conjugate symmetry. - Peter M. Maurer (Formal Methods Syst. Des., 2011)

Extending symmetric variable-pair transitivities using state-space transformations. - Peter M. Maurer (ACM Great Lakes Symposium on VLSI, 2012)

Metamorphic differential simulation using the multi-delay timing model. - Peter M. Maurer (SpringSim (TMS-DEVS), 2013)

A universal symmetry detection algorithm. - Peter M. Maurer (DATE, 2014)

Levelized compiled code multi-delay logic simulation. - Peter M. Maurer (SpringSim (TMS-DEVS), 2015)

A second look at oblivious simulation. - Peter M. Maurer (SummerSim, 2015)

Time-parallel multi-delay logic simulation. - Peter M. Maurer (SpringSim (TMS-DEVS), 2016)

Finite random variates using differential search trees. - Peter M. Maurer (SummerSim, 2017)

A nominal/inertial delay metamorphic differential simulator. - Peter M. Maurer (SummerSim, 2019)

Massive Generation of Data with Random Variates. - Peter M. Maurer (ANNSIM, 2021)

Computer Science Theory from a Practical Point of View. - Peter M. Maurer (CSCI, 2021)

Teaching Induction and Deductive Reasoning. - Peter M. Maurer (CSCI, 2022)

Generating Random XML Files Using DGL. - Peter M. Maurer; John Carbone (CSCI, 2022)

DGL Version 2 - Random Testing in the Mobile Computing Era. - Peter M. Maurer (SDSC, 2023)

Discrete random variates with finite support using differential search trees. - Peter M. Maurer (Simul., 2024)