How to Manage Complexity in Inter-Organizational Information Systems (IOIS) - Some Preliminary Conclusions. - Bengt E. W. Andersson; Peter Nilsson 001 (Decision Support in Public Administration, 1993)

A GSM speech coder implemented on a customized processor architecture. - Viktor Öwall; Pietro Andreani; L. Brange; Peter Nilsson 001; A. Wass; Mats Torkelson (ISCAS, 1993)

A Bit-Serial CMOS Digital IF-Filter for Mobile Radio Using an On-Chip Clock. - Peter Nilsson 001; Mats Torkelson; Kent Palmkvist; Mark Vesterbacka; Lars Wanhammar (Mobile Communications, 1994)

Design of a fast and area efficient filter. - Pontus Åström; Peter Nilsson 001; Mats Torkelson (EUSIPCO, 1996)

A monolithic digital clock-generator for on-chip clocking of custom DSP's. - Peter Nilsson 001; Mats Torkelson (IEEE J. Solid State Circuits, 1996)

A custom digital intermediate frequency filter for the American mobile telephone system. - Peter Nilsson 001; Mats Torkelson (IEEE J. Solid State Circuits, 1997)

Hardware implementation aspects of a detector based on successive interference cancellation in a DS/CDMA system. - Thomas Olsson 001; Carl Magnus Jönsson; Viktor Öwall; Peter Nilsson 001 (PIMRC, 1998)

An Efficient Implementation OF Bandlimited Dithering. - Scott A. Leyonhjelm; Michael Faulkner; Peter Nilsson 001 (Wirel. Pers. Commun., 1998)

Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. - Ahmed Hemani; Thomas Meincke; Shashi Kumar; Adam Postula; Thomas Olsson 001; Peter Nilsson 001; Johnny Öberg; Peeter Ellervee; Dan Lundqvist (DAC, 1999)

Silicon realization of an OFDM synchronization algorithm. - Stefan Johansson; Daniel Landström; Peter Nilsson 001 (ICECS, 1999)

Globally asynchronous locally synchronous architecture for large high-performance ASICs. - Thomas Meincke; Ahmed Hemani; Shashi Kumar; Peeter Ellervee; Johnny Öberg; Thomas Olsson 001; Peter Nilsson 001; Dan Lindqvist; Hannu Tenhunen (ISCAS (2), 1999)

An OFDM timing synchronization ASIC. - Stefan Johansson; Martin Nilsson; Peter Nilsson 001 (ICECS, 2000)

A digitally controlled low-power clock multiplier for globally asynchronous locally synchronous designs. - Thomas Olsson 001; Peter Nilsson 001; Thomas Meincke; Ahmad Hemami; Mats Torkelson (ISCAS, 2000)

Dual supply-voltage scaling for reconfigurable SoC's. - Thomas Olsson 001; Pontus Åström; Peter Nilsson 001 (ISCAS (3), 2001)

Application of Software design patterns to DSP library design. - Pontus Åström; Stefan Johansson; Peter Nilsson 001 (ISSS, 2001)

SOCWARE: A New Swedish Design Cluster for System-on-Chip. - Peter Nilsson 001; Petru Eles; Hannu Tenhunen (MSE, 2001)

A digitally controlled PLL for digital SOCs. - Thomas Olsson 001; Peter Nilsson 001 (ISCAS (5), 2003)

Teaching Digital HW-Design by Implementing a Complete MP3 Decoder. - Hugo Hedberg; Thomas Lenart; Henrik Svensson; Peter Nilsson 001; Viktor Öwall (MSE, 2003)

A VLSI implementation of MIMO detection for future wireless communications. - Zhan Guo; Peter Nilsson 001 (PIMRC, 2003)

A generic transmitter for wireless OFDM systems. - Fredrik Kristensen; Peter Nilsson 001; Anders Olsson (PIMRC, 2003)

VLSI implementation issues of lattice decoders for MIMO systems. - Zhan Guo; Peter Nilsson 001 (ISCAS (4), 2004)

Reduced complexity Schnorr-Euchner decoding algorithms for MIMO systems. - Zhan Guo; Peter Nilsson 001 (IEEE Commun. Lett., 2004)

A digitally controlled PLL for SoC applications. - Thomas Olsson 001; Peter Nilsson 001 (IEEE J. Solid State Circuits, 2004)

A 53.3 Mb/s 4×4 16-QAM MIMO decoder in 0.35-µm CMOS. - Zhan Guo; Peter Nilsson 001 (ISCAS (5), 2005)

A low complexity architecture for binary image erosion and dilation using structuring element decomposition. - Hugo Hedberg; Fredrik Kristensen; Peter Nilsson 001; Viktor Öwall (ISCAS (4), 2005)

Background Segmentation Beyond RGB. - Fredrik Kristensen; Peter Nilsson 001; Viktor Öwall (ACCV (2), 2006)

Arithmetic Reduction of the Static Power Consumption in Nanoscale CMOS. - Peter Nilsson 001 (ICECS, 2006)

Algorithm and implementation of the K-best sphere decoding for MIMO detection. - Zhan Guo; Peter Nilsson 001 (IEEE J. Sel. Areas Commun., 2006)

A VLSI Architecture of the Square Root Algorithm for V-BLAST Detection. - Zhan Guo; Peter Nilsson 001 (J. VLSI Signal Process., 2006)

Hardware architecture for matrix factorization in mimo receivers. - Barbara Cerato; Guido Masera; Peter Nilsson 001 (ACM Great Lakes Symposium on VLSI, 2007)

Reducing Leakage Power in Fixed Coefficient Arithmetic. - Peter Nilsson 001 (ICECS, 2007)

Arithmetic reduction of adder leakage in nanoscale CMOS. - Peter Nilsson 001 (APCCAS, 2008)

An Embedded Real-Time Surveillance System: Implementation and Evaluation. - Fredrik Kristensen; Hugo Hedberg; Hongtu Jiang; Peter Nilsson 001; Viktor Öwall (J. Signal Process. Syst., 2008)

Complexity reductions in unrolled CORDIC architectures. - Peter Nilsson 001 (ICECS, 2009)

Parabolic Synthesis Methodology Implemented on the Sine Function. - Erik Hertz; Peter Nilsson 001 (ISCAS, 2009)

Hardware Architecture of an SVD based MIMO OFDM Channel Estimator. - Johan Löfgren; Peter Nilsson 001; Ove Edfors (ISCAS, 2009)

Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS. - Peter Nilsson 001 (VLSI Design, 2009)

Automatic Discovery of Feature Sets for Dependency Parsing. - Peter Nilsson 001; Pierre Nugues (COLING, 2010)

Ultra low power hardware for computing Squared Euclidean Distances. - Peter Nilsson 001; Erik Hertz (ECCTD, 2011)

Power reductions in unrolled CORDIC architectures. - Peter Nilsson 001; Syed Nadeemuddin (ECCTD, 2011)

A VLSI implementation of logarithmic and exponential functions using a novel parabolic synthesis methodology compared to the CORDIC algorithm. - Peyman Pouyan; Erik Hertz; Peter Nilsson 001 (ECCTD, 2011)

Detecting multi-mode MIMO signals: Algorithm and architecture design. - Liang Liu 002; Peter Nilsson 001 (ISCAS, 2011)

Improved matching pursuit algorithm and architecture for LTE Channel Estimation. - Johan Löfgren; Ove Edfors; Peter Nilsson 001 (ISCAS, 2011)

Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain. - S. M. Yasser Sherazi; Peter Nilsson 001; Omer Can Akgun; Henrik Sjöland; Joachim Neves Rodrigues (ISCAS, 2011)

On hardware implementation of radix 3 and radix 5 FFT kernels for LTE systems. - Johan Löfgren; Peter Nilsson 001 (NORCHIP, 2011)

Low complexity soft-output signal detector for spatial-multiplexing MIMO system. - Liang Liu 002; Johan Löfgren; Peter Nilsson 001 (PIMRC, 2011)

A 100-fJ/cycle sub-VT decimation filter chain in 65 nm CMOS. - S. M. Yasser Sherazi; Peter Nilsson 001; Henrik Sjöland; Joachim Neves Rodrigues (ICECS, 2012)

A unified multi-mode MIMO detector with soft-output. - Liang Liu 002; Johan Löfgren; Peter Nilsson 001 (ISCAS, 2012)

A Receiver Architecture for Devices in Wireless Body Area Networks. - Henrik Sjöland; John B. Anderson; Carl Bryant; Rohit Chandra; Ove Edfors; Anders J. Johansson; Nafiseh Seyed Mazloum; Reza Meraji; Peter Nilsson 001; Dejan Radjen; Joachim Neves Rodrigues; S. M. Yasser Sherazi; et al. (IEEE J. Emerg. Sel. Topics Circuits Syst., 2012)

Area-Efficient Configurable High-Throughput Signal Detector Supporting Multiple MIMO Modes. - Liang Liu 002; Johan Löfgren; Peter Nilsson 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Low-Complexity Likelihood Information Generation for Spatial-Multiplexing MIMO Signal Detection. - Liang Liu 002; Johan Löfgren; Peter Nilsson 001 (IEEE Trans. Veh. Technol., 2012)

A high-speed QR decomposition processor for carrier-aggregated LTE-A downlink systems. - Rakesh Gangarajaiah; Liang Liu 002; Michal Stala; Peter Nilsson 001; Ove Edfors (ECCTD, 2013)

Power savings in digital filters for wireless communication. - Peter Nilsson 001; Anusha Gundarapu; S. M. Yasser Sherazi (ECCTD, 2013)

Ultra low energy design exploration of digital decimation filters in 65 nm dual-VT CMOS in the sub-VT domain. - S. M. Yasser Sherazi; Joachim Neves Rodrigues; Omer Can Akgun; Henrik Sjöland; Peter Nilsson 001 (Microprocess. Microsystems, 2013)

VLSI Implementation of a Soft-Output Signal Detector for Multimode Adaptive Multiple-Input Multiple-Output Systems. - Liang Liu 002; Johan Löfgren; Peter Nilsson 001; Viktor Öwall (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Lessons from ten years of the international master's program in System-on-Chip. - Peter Nilsson 001; Pietro Andreani; Krzysztof Kuchcinski; Joachim Rodrigues; Henrik Sjöland; Markus Törmänen; Lars-Erik Wernersson; Viktor Öwall (EWME, 2014)

Supply-voltage down conversion for digital CMOS designs. - Peter Nilsson 001; Mohammed Azher Ali; Manivannan Ethiraj; S. M. Yasser Sherazi (ICECS, 2014)

A digital baseband for low power FSK based receiver in 65 nm CMOS. - S. M. Yasser Sherazi; Henrik Sjöland; Peter Nilsson 001 (ICECS, 2014)

Ultra low power transceivers for wireless sensors and body area networks. - Henrik Sjöland; John B. Anderson; Carl Bryant; Rohit Chandra; Ove Edfors; Anders J. Johansson; Nafiseh Seyed Mazloum; Reza Meraji; Peter Nilsson 001; Dejan Radjen; Joachim Neves Rodrigues; S. M. Yasser Sherazi; et al. (ISMICT, 2014)

Hardware implementation of the exponential function using Taylor series. - Peter Nilsson 001; Ateeq Ur Rahman Shaik; Rakesh Gangarajaiah; Erik Hertz (NORCHIP, 2014)

Low complexity adaptive channel estimation and QR decomposition for an LTE-A downlink. - Rakesh Gangarajaiah; Peter Nilsson 001; Ove Edfors; Liang Liu 002 (PIMRC, 2014)

Improved Matching-Pursuit Implementation for LTE Channel Estimation. - Johan Löfgren; Liang Liu 002; Ove Edfors; Peter Nilsson 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Session 8 overview: Low-power digital techniques: Energy-efficient digital. - Victor V. Zyuban; Peter Nilsson 001 (ISSCC, 2015)

Low power unrolled CORDIC architectures. - Peter Nilsson 001; Yuhang Sun; Rakesh Gangarajaiah; Erik Hertz (NORCAS, 2015)

Combining the parabolic synthesis methodology with second-degree interpolation. - Erik Hertz; Bertil Svensson; Peter Nilsson 001 (Microprocess. Microsystems, 2016)

A Digitally Assisted Nonlinearity Mitigation System for Tunable Channel Select Filters. - Rakesh Gangarajaiah; Mohammed Abdulaziz; Henrik Sjöland; Peter Nilsson 001; Liang Liu 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

The Harmonized Parabolic Synthesis Methodology for Hardware Efficient Function Generation with Full Error Control. - Erik Hertz; Jingou Lai; Bertil Svensson; Peter Nilsson 001 (J. Signal Process. Syst., 2018)