A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. - Yohji Watanabe; Ring Wong; Toshiaki Kirihata; Daisuke Kato; John K. DeBrosse; Takahiko Rara; Munehiro Yoshida; Rideo Mukai; Khandker N. Quader; Takeshi Nagai; Peter Poechmueller; Peter Pfefferl; et al. (IEEE J. Solid State Circuits, 1996)

A 220-mm2, four- and eight-bank, 256-Mb SDRAM with single-sided stitched WL architecture. - Toshiaki Kirihata; Martin Gall; Kohji Hosokawa; Jean-Marc Dortu; Hing Wong; Peter Pfefferl; Brian L. Ji; Oliver Weinfurtner; John K. DeBrosse; Hartmud Terletzki; Manfred Selz; Wayne Ellis; et al. (IEEE J. Solid State Circuits, 1998)

23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applications. - Martin Brox; Mani Balakrishnan; Martin Broschwitz; Cristian Chetreanu; Stefan Dietrich; Fabien Funfrock; Marcos Alvarez Gonzalez; Thomas Hein; Eugen Huber; Daniel Lauber; Milena Ivanov; Maksim Kuzmenka; et al. (ISSCC, 2017)

An 8-Gb 12-Gb/s/pin GDDR5X DRAM for Cost-Effective High-Performance Applications. - Martin Brox; Mani Balakrishnan; Martin Broschwitz; Cristian Chetreanu; Stefan Dietrich; Fabien Funfrock; Marcos Alvarez Gonzalez; Thomas Hein; Eugen Huber; Daniel Lauber; Milena Ivanov; Maksim Kuzmenka; et al. (IEEE J. Solid State Circuits, 2018)