An approach for multilevel logic cell optimization in module generators. - Peter Poechmueller; Manfred Glesner (Great Lakes Symposium on VLSI, 1991)

HADES-high-level architecture development and exploration system. - Peter Poechmueller; Michael Held; Norbert Wehn; Manfred Glesner (Great Lakes Symposium on VLSI, 1991)

A CAD tool for designing large, fault-tolerant VLSI arrays. - Peter Poechmueller; G. K. Sharma 001; Manfred Glesner (Great Lakes Symposium on VLSI, 1991)

A New Approach for Designing Fault-Tolerant Array Processors. - Peter Poechmueller; Manfred Glesner (Fault-Tolerant Computing Systems, 1991)

High-level synthesis in a rapid-prototype environment for mechatronic systems. - Norbert Wehn; Hans-Jürgen Herpel; Thomas Hollstein; Peter Poechmueller; Manfred Glesner (EURO-DAC, 1992)

High Level Synthesis in an FPL-Based Computer Aided Prototyping Environment. - Peter Poechmueller; Hans-Jürgen Herpel; Manfred Glesner; Fang Longsen (FPL, 1992)

High-level synthesis transformations for programmable architectures. - Peter Poechmueller; Manfred Glesner; Fang Longsen (EURO-DAC, 1993)

Algorithmische Synthesetransformationen und deren Anwendung auf programmierbare Architekturen in mechatronischen Systemen. - Peter Pöchmüller (1993)

Fault-tolerant designs for 256 Mb DRAM. - Toshiaki Kirihata; Yohji Watanabe; Hing Wong; John K. DeBrosse; Munehiro Yoshida; Daisuke Kato; Shuso Fujii; Matthew R. Wordeman; Peter Poechmueller; Stephen A. Parke; Yoshiaki Asao (IEEE J. Solid State Circuits, 1996)

A 286 mm2 256 Mb DRAM with ×32 both-ends DQ. - Yohji Watanabe; Ring Wong; Toshiaki Kirihata; Daisuke Kato; John K. DeBrosse; Takahiko Rara; Munehiro Yoshida; Rideo Mukai; Khandker N. Quader; Takeshi Nagai; Peter Poechmueller; Peter Pfefferl; et al. (IEEE J. Solid State Circuits, 1996)

A 390-mm2, 16-bank, 1-Gb DDR SDRAM with hybrid bitline architecture. - Toshiaki Kirihata; Gerhard Mueller; Brian Ji; Gerd Frankowsky; Joseph M. Ross; Hartmud Terletzki; Dmitry G. Netis; Oliver Weinfurtner; David R. Hanson; Gabriel Daniel; Louis Lu-Chen Hsu; Daniel W. Storaska; et al. (IEEE J. Solid State Circuits, 1999)

An Analog Circuit Design and Optimization System With Rule-Guided Genetic Algorithm. - Ranran Zhou; Peter Poechmueller; Yong Wang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A 55-nm Three-Stage Operational Transconductance Amplifier With Single Cascode Miller Compensation for Large Capacitive Loads. - Ranran Zhou; Haozhe Wang 008; Peng Wang; Peter Poechmueller; Yong Wang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Semiconductor Application Fail Root Causes And Secure Test Remedy. - Heguo Yin; Peter Poechmueller (ETS, 2024)

Silent Data Corruption: DRAM Root Causes and Ways of Improving Test Quality Towards 0ppm. - Chenyu Fang; Peter Poechmueller (ETS, 2025)