CHERIvoke: Characterising Pointer Revocation using CHERI Capabilities for Temporal Memory Safety. - Hongyan Xia; Jonathan Woodruff; Sam Ainsworth; Nathaniel Wesley Filardo; Michael Roe; Alexander Richardson 001; Peter Rugg; Peter G. Neumann; Simon W. Moore; Robert N. M. Watson; Timothy M. Jones 001 (MICRO, 2019)

CompartOS: CHERI Compartmentalization for Embedded Systems. - Hesham Almatary; Michael Dodson; Jessica Clarke 001; Peter Rugg; Ivan Gomes; Michal Podhradsky; Peter G. Neumann; Simon W. Moore; Robert N. M. Watson (CoRR, 2022)

Architectural Contracts for Safe Speculation. - Franz A. Fuchs; Jonathan Woodruff; Peter Rugg; Marno van der Maas; Alexandre Joannou; Alexander Richardson 001; Jessica Clarke 001; Nathaniel Wesley Filardo; Brooks Davis; John Baldwin; Peter G. Neumann; Simon W. Moore; et al. (ICCD, 2023)

Cornucopia Reloaded: Load Barriers for CHERI Heap Temporal Safety. - Nathaniel Wesley Filardo; Brett F. Gutstein; Jonathan Woodruff; Jessica Clarke 001; Peter Rugg; Brooks Davis; Mark Johnston; Robert M. Norton; David Chisnall; Simon W. Moore; Peter G. Neumann; Robert N. M. Watson (ASPLOS (2), 2024)

A Suite of Processors to Explore CHERI-RISC-V Micro Architecture. - Peter Rugg; Jonathan Woodruff; Alexandre Joannou; Simon W. Moore (DSD, 2024)

Safe Speculation for Cheri. - Franz A. Fuchs; Jonathan Woodruff; Peter Rugg; Alexandre Joannou; Jessica Clarke 001; John Baldwin; Brooks Davis; Peter G. Neumann; Robert N. M. Watson; Simon W. Moore (ICCD, 2024)

Randomized Testing of RISC-V CPUs Using Direct Instruction Injection. - Alexandre Joannou; Peter Rugg; Jonathan Woodruff; Franz A. Fuchs; Marno van der Maas; Matthew Naylor; Michael Roe; Robert N. M. Watson; Peter G. Neumann; Simon W. Moore (IEEE Des. Test, 2024)

Adaptive CHERI Compartmentalization for Heterogeneous Accelerators. - Jianyi Cheng; A. Theodore Markettos; Alexandre Joannou; Paul Metzger; Matthew Naylor; Peter Rugg; Timothy M. Jones 001 (ISCA, 2025)