The IBM JBIG-ABIC Verification Suite. - Peter S. Colyer; Joan L. Mitchell (IBM J. Res. Dev., 1998)

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. - Subhendu Roy; David Z. Pan; Pavlos M. Mattheakis; Peter S. Colyer; Laurent Masse-Navette; Pierre-Olivier Ribet (ACM Great Lakes Symposium on VLSI, 2015)