A scalable high-frequency noise model for bipolar transistors with application to optimal transistor sizing for low-noise amplifier design. - Sorin P. Voinigescu; Michael C. Maliepaard; Jonathan L. Showell; Greg E. Babcock; David Marchesan; Michael Schröter; Peter Schvan; David L. Harame (IEEE J. Solid State Circuits, 1997)

A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier. - Yuriy M. Greshishchev; Peter Schvan (IEEE J. Solid State Circuits, 1999)

SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application. - Yuriy M. Greshishchev; Peter Schvan (IEEE J. Solid State Circuits, 2000)

A fully integrated SiGe receiver IC for 10-Gb/s data rate. - Yuriy M. Greshishchev; Peter Schvan; Jonathan L. Showell; Mu-Liang Xu; Jugnu J. Ojha; Jonathan E. Rogers (IEEE J. Solid State Circuits, 2000)

A 22GS/s 5b adc in 0.13µm SiGe BiCMOS. - Peter Schvan; Daniel Pollex; Shing-Chi Wang; Chris Falt; Naim Ben-Hamida (ISSCC, 2006)

CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design Examples. - Sorin P. Voinigescu; Sean T. Nicolson; Mehdi Khanpour; Keith K. W. Tang; Kenneth H. K. Yau; N. Seyedfathi; A. Timonov; A. Nachman; George V. Eleftheriades; Peter Schvan; Ming-Ta Yang (ISCAS, 2007)

Low-Voltage Topologies for 40-Gb/s Circuits in Nanoscale CMOS. - Theodoros Chalvatzis; Kenneth H. K. Yau; Ricardo Andres Aroca; Peter Schvan; Ming-Ta Yang; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2007)

Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio. - Terry Yao; Michael Q. Gordon; Keith K. W. Tang; Kenneth H. K. Yau; Ming-Ta Yang; Peter Schvan; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2007)

A 24GS/s 6b ADC in 90nm CMOS. - Peter Schvan; Jérôme Bach; Chris Falt; Philip Flemke; Robert Gibbins; Yuriy M. Greshishchev; Naim Ben-Hamida; Daniel Pollex; John Sitch; Shing-Chi Wang; John Wolczanski (ISSCC, 2008)

Clock recovery for a 40 Gb/s QPSK optical receiver. - Naim Ben-Hamida; John Sitch; Philip Flemke; Daniel Pollex; Peter Schvan; Yuriy M. Greshishchev; Shing-Chi Wang; Chris Falt (ICECS, 2009)

A 40 Gb/s transimpedance amplifier in 65 nm CMOS. - Samira Bashiri; Calvin Plett; Jorge Aguirre; Peter Schvan (ISCAS, 2010)

A 40GS/s 6b ADC in 65nm CMOS. - Yuriy M. Greshishchev; Jorge Aguirre; Marinette Besson; Robert Gibbins; Chris Falt; Philip Flemke; Naim Ben-Hamida; Daniel Pollex; Peter Schvan; Shing-Chi Wang (ISSCC, 2010)

A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. - Yuriy M. Greshishchev; Daniel Pollex; Shing-Chi Wang; Marinette Besson; Philip Flemeke; Stefan Szilagyi; Jorge Aguirre; Chris Falt; Naim Ben-Hamida; Robert Gibbins; Peter Schvan (ISSCC, 2011)

A 2.4-Vpp 60-Gb/s CMOS Driver With Digitally Variable Amplitude and Pre-Emphasis Control at Multiple Peaking Frequencies. - Ricardo Andres Aroca; Peter Schvan; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2011)

55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters. - James Hoffman; Stefan Shopov; Pascal Chevalier 002; Andreia Cathelin; Peter Schvan; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2016)

A 2x-Oversampling, 128-GS/s 5-bit Flash ADC for 64-GBaud Applications. - Alireza Zandieh; Peter Schvan; Sorin P. Voinigescu (BCICTS, 2018)

Coherent Transceiver for High Speed Optical Communications: Opportunities and Challenges. - Sebastien Blais; Yuriy M. Greshishchev; Peter Schvan; Ian Betty; Douglas McGhan (BCICTS, 2019)

Design of a 55-nm SiGe BiCMOS 5-bit Time-Interleaved Flash ADC for 64-Gbd 16-QAM Fiberoptics Applications. - Alireza Zandieh; Peter Schvan; Sorin P. Voinigescu (IEEE J. Solid State Circuits, 2019)

Data Converter Interleaving: Current Trends and Future Perspectives. - Christian Schmidt 001; Hiroshi Yamazaki; Gregory Raybon; Peter Schvan; Erwan Pincemin; S. J. Ben Yoo; Daniel J. Blumenthal; Takayuki Mizuno; Robert Elschner (IEEE Commun. Mag., 2020)

200-GS/s ADC Front-End Employing 25% Duty Cycle Quadrature Clock Generator. - Naftali Weiss; Gregory Cooke; Peter Schvan; Pascal Chevalier 002; Andreia Cathelin; Sorin P. Voinigescu (ESSCIRC, 2021)