A quadrisection-based combined place and route scheme for standard cells. - Peter Ramyalal Suaris; Gershon Kedem (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989)

A Methodology and Algorithms for Post-Placement Delay Optimization. - Lalgudi N. Kannan; Peter Suaris; Hong-Gee Fang (DAC, 1994)

Interface Timing Verification Drives System Design. - Ajay J. Daga; Peter Suaris (DAC, 1997)

Fast post-placement rewiring using easily detectable functional symmetries. - Chih-Wei Jim Chang; Chung-Kuan Cheng; Peter Suaris; Malgorzata Marek-Sadowska (DAC, 2000)

An algebraic multigrid solver for analytical placement with layout based clustering. - Hongyu Chen 001; Chung-Kuan Cheng; Nan-Chi Chou; Andrew B. Kahng; John F. MacDonald; Peter Suaris; Bo Yao 004; Zhengyong Zhu (DAC, 2003)

A physical retiming algorithm for field programmable gate arrays. - Peter Suaris; Dongsheng Wang 012; Pei-Ning Guo; Nan-Chi Chou (FPGA, 2003)

A Practical ASIC Methdology for Flexible Clock Tree Synthesis with Routing Blockages. - Dongsheng Wang 012; Peter Suaris; Nan-Chi Chou (PATMOS, 2003)

Fast adders in modern FPGAs. - Jianhua Liu; Michael Chang; Chung-Kuan Cheng; John F. MacDonald; Nan-Chi Chou; Peter Suaris (FPGA, 2004)

Incremental physical resynthesis for timing optimization. - Peter Suaris; Lung-Tien Liu; Yuzheng Ding; Nan-Chi Chou (FPGA, 2004)

A practical cut-based physical retiming algorithm for field programmable gate arrays. - Peter Suaris; Dongsheng Wang 012; Nan-Chi Chou (ASP-DAC, 2005)

The effect of post-layout pin permutation on timing. - Yuzheng Ding; Peter Suaris; Nan-Chi Chou (FPGA, 2005)

Total power-optimal pipelining and parallel processing under process variations in nanometer technology. - Peter Suaris; Taeho Kgil; Keith A. Bowman; Vivek De; Trevor N. Mudge (ICCAD, 2005)

Improving the efficiency of static timing analysis with false paths. - Shuo Zhou; Bo Yao 004; Hongyu Chen 001; Yi Zhu 002; Chung-Kuan Cheng; Michael D. Hutton; Truman Collins; Sridhar Srinivasan; Nan-Chi Chou; Peter Suaris (ICCAD, 2005)

Unified quadratic programming approach for mixed mode placement. - Bo Yao 004; Hongyu Chen 001; Chung-Kuan Cheng; Nan-Chi Chou; Lung-Tien Liu; Peter Suaris (ISPD, 2005)

Efficient Timing Analysis With Known False Paths Using Biclique Covering. - Shuo Zhou; Bo Yao 004; Hongyu Chen 001; Yi Zhu 002; Michael D. Hutton; Truman Collins; Sridhar Srinivasan; Nan-Chi Chou; Peter Suaris; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Application of 3-D ICs to FPGAs. - Peter Ramyalal Suaris (SLIP, 2010)