Constraint Solver for Generalized IC Layout. - Peter W. Cook (IBM J. Res. Dev., 1984)

Second-generation RISC floating point with multiply-add fused. - Erdem Hokenek; Robert K. Montoye; Peter W. Cook (IEEE J. Solid State Circuits, 1990)

Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor. - Phillip J. Restle; Keith A. Jenkins; Alina Deutsch; Peter W. Cook (IEEE J. Solid State Circuits, 1998)

An Adaptive Issue Queue for Reduced Power at High Performance. - Alper Buyuktosunoglu; Stanley Schuster; David M. Brooks; Pradip Bose; Peter W. Cook; David H. Albonesi (PACS, 2000)

Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. - David M. Brooks; Pradip Bose; Stanley Schuster; Hans M. Jacobson; Prabhakar Kudva; Alper Buyuktosunoglu; John-David Wellman; Victor V. Zyuban; Manish Gupta; Peter W. Cook (IEEE Micro, 2000)

A circuit level implementation of an adaptive issue queue for power-aware microprocessors. - Alper Buyuktosunoglu; David H. Albonesi; Stanley Schuster; David M. Brooks; Pradip Bose; Peter W. Cook (ACM Great Lakes Symposium on VLSI, 2001)

Synchronous Interlocked Pipelines. - Hans M. Jacobson; Prabhakar Kudva; Pradip Bose; Peter W. Cook; Stanley Schuster (ASYNC, 2002)

Tradeoffs in power-efficient issue queue design. - Alper Buyuktosunoglu; David H. Albonesi; Pradip Bose; Peter W. Cook; Stanley Schuster (ISLPED, 2002)

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. - Pradip Bose; David M. Brooks; Alper Buyuktosunoglu; Peter W. Cook; K. Das; Philip G. Emma; Michael Gschwind; Hans M. Jacobson; Tejas Karkhanis; Prabhakar Kudva; Stanley Schuster; James E. Smith 001; et al. (PACS, 2002)

New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology. - Koushik K. Das; Rajiv V. Joshi; Ching-Te Chuang; Peter W. Cook; Richard B. Brown (ESSCIRC, 2003)

New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. - Koushik K. Das; Rajiv V. Joshi; Ching-Te Chuang; Peter W. Cook; Richard B. Brown (ISLPED, 2003)

Dynamically Tuning Processor Resources with Adaptive Processing. - David H. Albonesi; Rajeev Balasubramonian; Steve Dropsho; Sandhya Dwarkadas; Eby G. Friedman; Michael C. Huang 001; Volkan Kursun; Grigorios Magklis; Michael L. Scott; Greg Semeraro; Pradip Bose; Alper Buyuktosunoglu; et al. (Computer, 2003)

Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz. - Stanley Schuster; Peter W. Cook (IEEE J. Solid State Circuits, 2003)