SIMD Neural Net Mapping on MIMD Architectures. - Peter Wohl; Thomas W. Christopher (ICPP (1), 1990)

Parallel Conceptual Clustering through Message-Driven Computing. - Peter Wohl; Thomas W. Christopher (ICPP (2), 1991)

MIMD implementation of neural networks through pipelined, parallel communication trees. - Peter Wohl; Thomas W. Christopher (ICTAI, 1991)

A Parallel Processing Approach to Incremental Conceptual Clustering. - Peter Wohl; Thomas W. Christopher (IPPS, 1991)

Designing Conceptual Clustering for Parallel Implementation. - Peter Wohl; Thomas W. Christopher (ICPP (3), 1992)

Efficiency through Reduced Communication in Message Passing Simulation of Neural Networks. - Peter Wohl (Int. J. Artif. Intell. Tools, 1993)

Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates. - Peter Wohl; John A. Waicukauski (ITC, 1996)

Testing "untestable" faults in three-state circuits. - Peter Wohl; John A. Waicukauski; Matthew Graf (VTS, 1996)

A Unified Interface for Scan Test Generation Based on STIL. - Peter Wohl; John A. Waicukauski (ITC, 1997)

Using ATPG for clock rules checking in complex scan design. - Peter Wohl; John A. Waicukauski (VTS, 1997)

Extracting gate-level networks from simulation tables. - Peter Wohl; John A. Waicukauski (ITC, 1998)

Defining ATPG rules checking in STIL. - Peter Wohl; John A. Waicukauski (ITC, 1998)

Output in still, input in still. - Peter Wohl (ITC, 1999)

Using Verilog simulation libraries for ATPG. - Peter Wohl; John A. Waicukauski (ITC, 1999)

Optimizing the flattened test-generation model for very large designs. - Peter Wohl; John A. Waicukauski (ITC, 2000)

P1450.1: STIL for the Simulation Environmen. - Peter Wohl; Nathan Biggs (VTS, 2000)

Design of compactors for signature-analyzers in built-in self-test. - Peter Wohl; John A. Waicukauski; Thomas W. Williams (ITC, 2001)

Effective diagnostics through interval unloads in a BIST environment. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Gregory A. Maston (DAC, 2002)

Efficient compression and application of deterministic patterns in a logic BIST architecture. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Minesh B. Amin (DAC, 2003)

X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Minesh B. Amin (ITC, 2003)

Analysis and Design of Optimal Combinational Compactors. - Peter Wohl; Leendert M. Huisman (VTS, 2003)

Scalable selector architecture for x-tolerant deterministic BIST. - Peter Wohl; John A. Waicukauski; Sanjay Patel (DAC, 2004)

Efficient compression of deterministic patterns into multiple PRPG seeds. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Francisco DaSilva; Thomas W. Williams; Rohit Kapur (ITC, 2005)

Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST. - Peter Wohl; John A. Waicukauski; Sanjay Patel; Cy Hay; Emil Gizdarski; Ben Mathew (VTS, 2005)

Fully X-tolerant combinational scan compression. - Peter Wohl; John A. Waicukauski; Sanjay Ramnath (ITC, 2007)

Minimizing the Impact of Scan Compression. - Peter Wohl; John A. Waicukauski; Rohit Kapur; Sanjay Ramnath; Emil Gizdarski; Thomas W. Williams; P. Jaini (VTS, 2007)

Automated Design and Insertion of Optimal One-Hot Bus Encoders. - Peter Wohl; John A. Waicukauski; Sanjay Patel (VTS, 2007)

DFT MAX and Power. - Rohit Kapur; T. Finklea; Felix Ng; Anshuman Chandra; Sanjay Ramnath; Peter Wohl; Thomas W. Williams; Ashok Anbalan; Sandeep S. Kulkarni; Tammy Fernandes; Pramod Notiyath; Rajesh Uppuluri (J. Low Power Electron., 2007)

Increasing Scan Compression by Using X-chains. - Peter Wohl; John A. Waicukauski; Frederic Neuveux (ITC, 2008)

Fully X-tolerant, very high scan compression. - Peter Wohl; John A. Waicukauski; Frederic Neuveux; Emil Gizdarski (DAC, 2010)

Highly efficient parallel ATPG based on shared memory. - X. Cai; Peter Wohl; John A. Waicukauski; Pramod Notiyath (ITC, 2010)

Increasing PRPG-based compression by delayed justification. - Peter Wohl; John A. Waicukauski; T. Finklea (ITC, 2010)

Hybrid selector for high-X scan compression. - Peter Wohl; John A. Waicukauski; Frederic Neuveux; Jonathon E. Colburn (ITC, 2012)

Enhancing testability by structured partial scan. - Peter Wohl; John A. Waicukauski; Jonathon E. Colburn (VTS, 2012)

A distributed-multicore hybrid ATPG system. - X. Cai; Peter Wohl (ITC, 2013)

Two-level compression through selective reseeding. - Peter Wohl; John A. Waicukauski; Frederic Neuveux; Gregory A. Maston; Nadir Achouri; Jonathon E. Colburn (ITC, 2013)

Improving test generation by use of majority gates. - Peter Wohl; John A. Waicukauski (VTS, 2013)

Fault sharing in a copy-on-write based ATPG system. - X. Cai; Peter Wohl; Daniel Martin 002 (ITC, 2014)

Achieving extreme scan compression for SoC Designs. - Peter Wohl; John A. Waicukauski; Jonathon E. Colburn; Milind Sonawane (ITC, 2014)

A New Paradigm for Synthesis of Linear Decompressors. - Emil Gizdarski; Peter Wohl; John A. Waicukauski (DAC, 2017)

XLBIST: X-Tolerant Logic BIST. - Peter Wohl; John A. Waicukauski; Gregory A. Maston; Jonathon E. Colburn (ITC, 2018)