Model-based fault diagnosis of sequential circuits and its acceleration. - Benjamin Rogel-Favila; Antony Wakeling; Peter Y. K. Cheung (EURO-DAC, 1991)

A Tag Coprocessor Architecture for Symbolic Languages. - Vicente Fuentes-Sánchez; Peter Y. K. Cheung (ICCD, 1991)

A New Schematic-driven Floorplanning Algorithm for Analog Cell Layout. - Nasir-ud-Din Gohar; Peter Y. K. Cheung (ISCAS, 1993)

A Model-based Approach to Analog Fault Diagnosis using Techniques from Optimisation. - Salman Ahmed; Peter Y. K. Cheung; Phil Collins (EDAC-ETC-EUROASIC, 1994)

Area & Time Limitations of FPGA-based Virtual Hardware. - Osama T. Albaharna; Peter Y. K. Cheung; Thomas J. Clarke (ICCD, 1994)

Analog Fault Diagnosis - A Practical Approach. - Salman Ahmed; Peter Y. K. Cheung (ISCAS, 1994)

Virtual Hardware and the Limits of Computational Speed-up. - Osama T. Albaharna; Peter Y. K. Cheung; Thomas J. Clarke (ISCAS, 1994)

A Method of Representative Fault Selection in Digital Circuits for ATPG. - Akachai Sang-In; Peter Y. K. Cheung (ISCAS, 1994)

Combining goal-directed, reactive and reflexive navigation in autonomous mobile robots. - Majd Alwan; Peter Y. K. Cheung; Akram Saleh; Nour E. Cheikh Obeid (ANZIIS, 1996)

An incremental machine learning mechanism applied to robot navigation. - Nawwaf N. Kharma; Majd Alwan; Peter Y. K. Cheung (ANZIIS, 1996)

Realistic Fault Extraction for Boards. - José T. de Sousa; T. Shen; Peter Y. K. Cheung (ED&TC, 1996)

On the viability of FPGA-based integrated coprocessors. - Osama T. Albaharna; Peter Y. K. Cheung; Thomas J. Clarke (FCCM, 1996)

Modelling and optimising run-time reconfigurable systems. - Wayne Luk; Nabeel Shirazi; Peter Y. K. Cheung (FCCM, 1996)

Adaptive Automatic Facial Feature Segmentation. - Hasan Demirel; Thomas J. Clarke; Peter Y. K. Cheung (FG, 1996)

Hierarchical tolerance analysis using statistical behavioral models. - Timo Koskinen; Peter Y. K. Cheung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A Quasi Delay-Insensitive Bus Proposal for Asynchronous Systems. - Pedro A. Molina; Peter Y. K. Cheung (ASYNC, 1997)

Improved diagnosis of realistic interconnect shorts. - José T. de Sousa; Peter Y. K. Cheung (ED&TC, 1997)

Compilation tools for run-time reconfigurable designs. - Wayne Luk; Nabeel Shirazi; Peter Y. K. Cheung (FCCM, 1997)

A reconfigurable data-localised array for morphological algorithms. - Anjit Sekhar Chaudhuri; Peter Y. K. Cheung; Wayne Luk (FPL, 1997)

Pipeline morphing and virtual pipelines. - Wayne Luk; Nabeel Shirazi; Shaori Guo; Peter Y. K. Cheung (FPL, 1997)

Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. - Patrick I. Mackinlay; Peter Y. K. Cheung; Wayne Luk; Richard Sandiford (FPL, 1997)

Asnchronous Wrapper for Heterogeneous Systems. - David S. Bormann; Peter Y. K. Cheung (ICCD, 1997)

Diagnosis of Boards for Realistic Interconnect Shorts. - José T. de Sousa; Peter Y. K. Cheung (J. Electron. Test., 1997)

Modelling and Handling Uncertainties in Mobile Robotics. - Majd Alwan; Peter Y. K. Cheung (J. Intell. Fuzzy Syst., 1997)

A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. - Simon D. Haynes; Peter Y. K. Cheung (FCCM, 1998)

Automating Production of Run-Time Reconfigurable Designs. - Nabeel Shirazi; Wayne Luk; Peter Y. K. Cheung (FCCM, 1998)

Run-Time Management of Dynamically Recongigurable Designs. - Nabeel Shirazi; Wayne Luk; Peter Y. K. Cheung (FPL, 1998)

Algorithms and Structures for Reconfigurable Multiplication Units. - Simon D. Haynes; Antonio B. Ferrari; Peter Y. K. Cheung (SBCCI, 1998)

Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs. - Simon D. Haynes; Antonio B. Ferrari; Peter Y. K. Cheung (CICC, 1999)

SONIC - A Plug-In Architecture for Video Processing. - Simon D. Haynes; Peter Y. K. Cheung; Wayne Luk; John Stone (FCCM, 1999)

Reconfigurable Computing for Augmented Reality. - Wayne Luk; T. K. Lee; J. Rice; Nabeel Shirazi; Peter Y. K. Cheung (FCCM, 1999)

Synthia: Synthesis of Interacting Automata Targeting LUT-based FPGAs. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (FPL, 1999)

Quantitative Analysis of Run-Time Reconfigurable Database Search. - Nabeel Shirazi; Wayne Luk; Dan Benyamin; Peter Y. K. Cheung (FPL, 1999)

Flexible instruction processors. - Shay Ping Seng; Wayne Luk; Peter Y. K. Cheung (CASES, 2000)

Multiple Precision for Resource Minimization. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (FCCM, 2000)

Multiple-Wordlength Resource Binding. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (FPL, 2000)

Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. - Jörn Gause; Peter Y. K. Cheung; Wayne Luk (FPL, 2000)

Roundoff-noise shaping in filter design. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (ISCAS, 2000)

Video Image Processing with the Sonic Architecture. - Simon D. Haynes; John Stone; Peter Y. K. Cheung; Wayne Luk (Computer, 2000)

Heuristic datapath allocation for multiple wordlength systems. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (DATE, 2001)

The Multiple Wordlength Paradigm. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (FCCM, 2001)

The Effect of FPGA Granularity on Video Codec Implementations. - Jörn Gause; Carsten Reuter; Holger Kropp; Peter Y. K. Cheung; Wayne Luk (FCCM, 2001)

A Digit-Serial Structure for Reconfigurable Multipliers. - Chakkapas Visavakul; Peter Y. K. Cheung; Wayne Luk (FPL, 2001)

MASH delta-sigma modulators for wideband and multi-standard applications. - Kei-Tee Tiew; Alison J. Payne; Peter Y. K. Cheung (ISCAS (4), 2001)

Quantitative Analysis of FPGA-based Database Searching. - Nabeel Shirazi; Dan Benyamin; Wayne Luk; Peter Y. K. Cheung; Shaori Guo (J. VLSI Signal Process., 2001)

Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory. - Sambuddhi Hettiaratchi; Peter Y. K. Cheung; Thomas J. W. Clarke (DATE, 2002)

Optimum Wordlength Allocation. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (FCCM, 2002)

Customising Floating-Point Designs. - Altaf Abdul Gaffar; Wayne Luk; Peter Y. K. Cheung; Nabeel Shirazi (FCCM, 2002)

Reconfigurable Shape-Adaptive Template Matching Architectures. - Jörn Gause; Peter Y. K. Cheung; Wayne Luk (FCCM, 2002)

Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. - Wim J. C. Melis; Peter Y. K. Cheung; Wayne Luk (FCCM, 2002)

Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. - Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk (FCCM, 2002)

Automating Customisation of Floating-Point Designs. - Altaf Abdul Gaffar; Wayne Luk; Peter Y. K. Cheung; Nabeel Shirazi; James Hwang (FPL, 2002)

Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. - Wim J. C. Melis; Peter Y. K. Cheung; Wayne Luk (FPL, 2002)

Run-Time Adaptive Flexible Instruction Processors. - Shay Ping Seng; Wayne Luk; Peter Y. K. Cheung (FPL, 2002)

Floating-point bitwidth analysis via automatic differentiation. - Altaf Abdul Gaffar; Oskar Mencer; Wayne Luk; Peter Y. K. Cheung; Nabeel Shirazi (FPT, 2002)

Strassen's matrix multiplication for customisable processors. - Henry M. D. Ip; James D. Low; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk; Shay Ping Seng; Paul Metzgen (FPT, 2002)

Incremental programming for reconfigurable engines. - Dong-U Lee; T. K. Lee; Wayne Luk; Peter Y. K. Cheung (FPT, 2002)

PD-XML: extensible markup language for processor description. - Shay Ping Seng; Krishna V. Palem; Rodric M. Rabbah; Weng-Fai Wong; Wayne Luk; Peter Y. K. Cheung (FPT, 2002)

Energy efficient address assignment through minimized memory row switching. - Sambuddhi Hettiaratchi; Peter Y. K. Cheung; Thomas J. W. Clarke (ICCAD, 2002)

Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. - Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk (Des. Autom. Embed. Syst., 2002)

Mesh Partitioning Approach to Energy Efficient Data Layout. - Sambuddhi Hettiaratchi; Peter Y. K. Cheung (DATE, 2003)

A Hardware Gaussian Noise Generator for Channel Code Evaluation. - Dong-U Lee; Wayne Luk; John D. Villasenor; Peter Y. K. Cheung (FCCM, 2003)

Non-uniform Segmentation for Hardware Function Evaluation. - Dong-U Lee; Wayne Luk; John D. Villasenor; Peter Y. K. Cheung (FPL, 2003)

Globally Asynchronous Locally Synchronous FPGA Architectures. - Andrew Royal; Peter Y. K. Cheung (FPL, 2003)

A Reconfigurable Platform for Real-Time Embedded Video Image Processing. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (FPL, 2003)

A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. - Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk (FPL, 2003)

Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. - Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk (FPL, 2003)

High-level language extensions for run-time reconfigurable systems. - T. K. Lee; Arran Derbyshire; Wayne Luk; Peter Y. K. Cheung (FPT, 2003)

Hierarchical segmentation schemes for function evaluation. - Dong-U Lee; Wayne Luk; John D. Villasenor; Peter Y. K. Cheung (FPT, 2003)

Architectures for function evaluation on FPGAs. - Nalin Sidahao; George A. Constantinides; Peter Y. K. Cheung (ISCAS (2), 2003)

Multitasking in hardware-software codesign for reconfigurable computer. - Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk (ISCAS (5), 2003)

SONICmole: a debugging environment for the UltraSONIC reconfigurable computer. - Theerayod Wiangtong; Chun Te Ewe; Peter Y. K. Cheung (ISCAS (2), 2003)

Wordlength optimization for linear digital signal processing. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Synthesis of saturation arithmetic architectures. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (ACM Trans. Design Autom. Electr. Syst., 2003)

Synthesis and optimization of DSP algorithms. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (Kluwer, 2004)

A Novel Implementation of Tile-Based Address Mapping. - Sambuddhi Hettiaratchi; Peter Y. K. Cheung (DATE, 2004)

Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. - Tero Rissa; Wayne Luk; Peter Y. K. Cheung (ERSA, 2004)

Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. - Altaf Abdul Gaffar; Oskar Mencer; Wayne Luk; Peter Y. K. Cheung (FCCM, 2004)

Migrating Functionality from ROMS to Embedded Multipliers. - Gareth W. Morris; George A. Constantinides; Peter Y. K. Cheung (FCCM, 2004)

A Structured System Methodology for FPGA Based System-on-A-Chip Design. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (FCCM, 2004)

A Steerable Complex Wavelet Construction and Its Implementation on FPGA. - Christos-Savvas Bouganis; Peter Y. K. Cheung; Jeffrey Ng; Anil A. Bharath (FPL, 2004)

BIST Based Interconnect Fault Location for FPGAs. - Nicola Campregher; Peter Y. K. Cheung; Milan Vasilko (FPL, 2004)

Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. - Chun Te Ewe; Peter Y. K. Cheung; George A. Constantinides (FPL, 2004)

SoftSONIC: A Customisable Modular Platform for Video Applications. - Tero Rissa; Peter Y. K. Cheung; Wayne Luk (FPL, 2004)

A Structured Methodology for System-on-an-FPGA Design. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (FPL, 2004)

Multiple Restricted Multiplication. - Nalin Sidahao; George A. Constantinides; Peter Y. K. Cheung (FPL, 2004)

A scalable hardware architecture for prime number validation. - Ray C. C. Cheung; Ashley Brown; Wayne Luk; Peter Y. K. Cheung (FPT, 2004)

Scalable structured data access by combining autonomous memory blocks. - Wim J. C. Melis; Peter Y. K. Cheung; Wayne Luk (FPT, 2004)

Autonomous Memory Block for reconfigurable computing. - Wim J. C. Melis; Peter Y. K. Cheung; Wayne Luk (ISCAS (2), 2004)

Guest Editors' Introduction: Field Programmable Logic and Applications. - Peter Y. K. Cheung; George A. Constantinides; José T. de Sousa (IEEE Trans. Computers, 2004)

A Gaussian Noise Generator for Hardware-Based Simulations. - Dong-U Lee; Wayne Luk; John D. Villasenor; Peter Y. K. Cheung (IEEE Trans. Computers, 2004)

Automating custom-precision function evaluation for embedded processors. - Ray C. C. Cheung; Dong-U Lee; Oskar Mencer; Wayne Luk; Peter Y. K. Cheung (CASES, 2005)

Reconfigurable Elliptic Curve Cryptosystems on a Chip. - Ray C. C. Cheung; Wayne Luk; Peter Y. K. Cheung (DATE, 2005)

Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. - Suhaib A. Fahmy; Peter Y. K. Cheung; Wayne Luk (DATE, 2005)

Cell Based Motion Estimators for Reconfigurable Platforms. - Wim J. C. Melis; Kieron Turkington; Alexander Whitton; Wayne Luk; Peter Y. K. Cheung; Paul Metzgen (ERSA, 2005)

A Novel 2D Filter Design Methodology for Heterogeneous Devices. - Christos-Savvas Bouganis; George A. Constantinides; Peter Y. K. Cheung (FCCM, 2005)

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs. - Nicola Campregher; Peter Y. K. Cheung; George A. Constantinides; Milan Vasilko (FPGA, 2005)

Exploration of heterogeneous reconfigurable architectures (abstract only). - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (FPGA, 2005)

Heterogeneity Exploration for Multiple 2D Filter Designs. - Christos-Savvas Bouganis; Peter Y. K. Cheung; George A. Constantinides (FPL, 2005)

Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. - Nicola Campregher; Peter Y. K. Cheung; George A. Constantinides; Milan Vasilko (FPL, 2005)

Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. - Chun Te Ewe; Peter Y. K. Cheung; George A. Constantinides (FPL, 2005)

Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. - Suhaib A. Fahmy; Peter Y. K. Cheung; Wayne Luk (FPL, 2005)

Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. - Gareth W. Morris; George A. Constantinides; Peter Y. K. Cheung (FPL, 2005)

Power and Area Optimization for Multiple Restricted Multiplication. - Nalin Sidahao; George A. Constantinides; Peter Y. K. Cheung (FPL, 2005)

An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (FPL, 2005)

Have GPUs Made FPGAs Redundant in the Field of Video Processing? - Ben Cope; Peter Y. K. Cheung; Wayne Luk; Sarah Witt (FPT, 2005)

FPGA Based Router for Cognitive Packet Networks. - Laurence A. Hey; Peter Y. K. Cheung; Michael Gellman (FPT, 2005)

A novel 2D filter design methodology. - Christos-Savvas Bouganis; George A. Constantinides; Peter Y. K. Cheung (ISCAS (1), 2005)

A heuristic approach for multiple restricted multiplication. - Nalin Sidahao; George A. Constantinides; Peter Y. K. Cheung (ISCAS (1), 2005)

Hardware/software codesign: a systematic approach targeting data-intensive applications. - Theerayod Wiangtong; Peter Y. K. Cheung; Wayne Luk (IEEE Signal Process. Mag., 2005)

Customizable elliptic curve cryptosystems. - Ray C. C. Cheung; N. J. Telle; Wayne Luk; Peter Y. K. Cheung (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Optimum and heuristic synthesis of multiple word-length architectures. - George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2005)

A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. - Su-Shin Ang; George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (ARC, 2006)

A novel FPGA-based implementation of time adaptive clustering for logical story unit segmentation. - Sutjipto Arifin; Peter Y. K. Cheung (DATE Designers' Forum, 2006)

Hardware efficient architectures for Eigenvalue computation. - Yang Liu; Christos-Savvas Bouganis; Peter Y. K. Cheung; Philip Heng Wai Leong; Stephen J. Motley (DATE, 2006)

A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design. - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (FCCM, 2006)

Yield enhancements of design-specific FPGAs. - Nicola Campregher; Peter Y. K. Cheung; George A. Constantinides; Milan Vasilko (FPGA, 2006)

Towards Affective Level Video Applications: A Novel FPGA-Based Video Arousal Content Modeling System. - Sutjipto Arifin; Peter Y. K. Cheung (FPL, 2006)

FPGA-Accelerated Pre-Attentive Segmentation in Primary Visual Cortex. - Christos-Savvas Bouganis; Peter Y. K. Cheung; Zhaoping Li 001 (FPL, 2006)

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs. - Nicola Campregher; Peter Y. K. Cheung; George A. Constantinides; Milan Vasilko (FPL, 2006)

Efficient Realtime FPGA Implementation of the Trace Transform. - Suhaib A. Fahmy; Christos-Savvas Bouganis; Peter Y. K. Cheung; Wayne Luk (FPL, 2006)

On-FPGA Communication Architectures and Design Factors. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPL, 2006)

A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design. - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (FPL, 2006)

The cost of data dependence in motion vector estimation for reconfigurable platforms. - Su-Shin Ang; George A. Constantinides; Wayne Luk; Peter Y. K. Cheung (FPT, 2006)

A comparison of 2-D discrete wavelet transform computation schedules on FPGAs. - Maria E. Angelopoulou; Konstantinos Masselos; Peter Y. K. Cheung; Yiannis Andreopoulos (FPT, 2006)

A statistical framework for dimensionality reduction implementation in FPGAs. - Christos-Savvas Bouganis; Iosifina Pournara; Peter Y. K. Cheung (FPT, 2006)

Within-die delay variability in 90nm FPGAs and beyond. - N. Pete Sedcole; Peter Y. K. Cheung (FPT, 2006)

User Attention Based Arousal Content Modeling. - Sutjipto Arifin; Peter Y. K. Cheung (ICIP, 2006)

A Spatiotemporal Saliency Framework. - Yang Liu; Christos-Savvas Bouganis; Peter Y. K. Cheung (ICIP, 2006)

Fast word-level power models for synthesis of FPGA-based arithmetic. - Jonathan A. Clarke; Altaf Abdul Gaffar; George A. Constantinides; Peter Y. K. Cheung (ISCAS, 2006)

On-Chip Communication in Run-Time Assembled Reconfigurable Systems. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (ICSAMOS, 2006)

Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits. - Gabriel Caffarena; George A. Constantinides; Peter Y. K. Cheung; Carlos Carreras; Octavio Nieto-Taladriz (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. - Ben Cope; Peter Y. K. Cheung; Wayne Luk (ASAP, 2007)

A Hybrid Memory Sub-system for Video Coding Applications. - Su-Shin Ang; George A. Constantinides; Wayne Luk; Peter Y. K. Cheung (FCCM, 2007)

Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. - Tobias Becker; Wayne Luk; Peter Y. K. Cheung (FCCM, 2007)

Efficient Mapping of Dimensionality Reduction Designs onto Heterogeneous FPGAs. - Christos-Savvas Bouganis; Iosifina Pournara; Peter Y. K. Cheung (FCCM, 2007)

Automatic On-chip Memory Minimization for Data Reuse. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (FCCM, 2007)

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis. - N. Pete Sedcole; Peter Y. K. Cheung (FPGA, 2007)

On the feasibility of early routing capacitance estimation for FPGAs. - Jonathan A. Clarke; George A. Constantinides; Peter Y. K. Cheung (FPL, 2007)

Efficient mapping of a Kalman filter into an FPGA using Taylor Expansion. - Yang Liu; Christos-Savvas Bouganis; Peter Y. K. Cheung (FPL, 2007)

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction. - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (FPT, 2007)

Self-characterization of Combinatorial Circuit Delays in FPGAs. - Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (FPT, 2007)

A Novel Video Parsing Algorithm Utilizing the Pleasure-Arousal-Dominance Emotional Information. - Sutjipto Arifin; Peter Y. K. Cheung (ICIP (6), 2007)

A computation method for video segmentation utilizing the pleasure-arousal-dominance emotional information. - Sutjipto Arifin; Peter Y. K. Cheung (ACM Multimedia, 2007)

A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk; Kai-Pui Lam (NOCS, 2007)

A Novel Probabilistic Approach to Modeling the Pleasure-Arousal-Dominance Content of the Video based on "Working Memory". - Sutjipto Arifin; Peter Y. K. Cheung (ICSC, 2007)

ROM to DSP block transfer for resource constrained synthesis. - Gareth W. Morris; George A. Constantinides; Peter Y. K. Cheung (IET Comput. Digit. Tech., 2007)

Real-time hardware acceleration of the trace transform. - Suhaib A. Fahmy; Christos-Savvas Bouganis; Peter Y. K. Cheung; Wayne Luk (J. Real Time Image Process., 2007)

Run-Time Integration of Reconfigurable Video Processing Systems. - N. Pete Sedcole; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk (IEEE Trans. Very Large Scale Integr. Syst., 2007)

FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor. - Maria E. Angelopoulou; Christos-Savvas Bouganis; Peter Y. K. Cheung; George A. Constantinides (ARC, 2008)

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (BCS Int. Acad. Conf., 2008)

Using Reconfigurable Logic to Optimise GPU Memory Accesses. - Ben Cope; Peter Y. K. Cheung; Wayne Luk (DATE, 2008)

High-throughput interconnect wave-pipelining for global communication in FPGAs. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPGA, 2008)

Measuring and modeling FPGA clock variability. - N. Pete Sedcole; Justin S. J. Wong; Peter Y. K. Cheung (FPGA, 2008)

Towards benchmarking energy efficiency of reconfigurable architectures. - Tobias Becker; Peter Jamieson; Wayne Luk; Peter Y. K. Cheung; Tero Rissa (FPL, 2008)

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (FPL, 2008)

Fault tolerant methods for reliability in FPGAs. - Edward A. Stott; N. Pete Sedcole; Peter Y. K. Cheung (FPL, 2008)

Combating process variation on FPGAS with a precise at-speed delay measurement method. - Justin S. J. Wong; Peter Y. K. Cheung; N. Pete Sedcole (FPL, 2008)

Wave-pipelined signaling for on-FPGA communication. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (FPT, 2008)

Modelling and compensating for clock skew variability in FPGAs. - N. Pete Sedcole; Justin S. J. Wong; Peter Y. K. Cheung (FPT, 2008)

Co-optimisation of datapath and memory in outer loop pipelining. - Kieron Turkington; George A. Constantinides; Peter Y. K. Cheung; Konstantinos Masselos (FPT, 2008)

A transition probability based delay measurement method for arbitrary circuits on FPGAs. - Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (FPT, 2008)

Video enhancement on an adaptive image sensor. - Maria E. Angelopoulou; Christos-Savvas Bouganis; Peter Y. K. Cheung (ICIP, 2008)

Glitch-aware output switching activity from word-level statistics. - Jonathan A. Clarke; George A. Constantinides; Peter Y. K. Cheung; Alastair M. Smith (ISCAS, 2008)

Characterisation of FPGA Clock Variability. - N. Pete Sedcole; Justin S. J. Wong; Peter Y. K. Cheung (ISVLSI, 2008)

Implementation of Wave-Pipelined Interconnects in FPGAs. - Terrence S. T. Mak; Crescenzo D'Alessandro; N. Pete Sedcole; Peter Y. K. Cheung; Alexandre Yakovlev; Wayne Luk (NOCS, 2008)

Systematic design space exploration for customisable multi-processor architectures. - Ben Cope; Peter Y. K. Cheung; Wayne Luk (ICSAMOS, 2008)

Global interconnections in FPGAs: modeling and performance analysis. - Terrence S. T. Mak; Crescenzo D'Alessandro; N. Pete Sedcole; Peter Y. K. Cheung; Alexandre Yakovlev; Wayne Luk (SLIP, 2008)

Interconnection lengths and delays estimation for communication links in FPGAs. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (SLIP, 2008)

Comments on the BCS Lecture "The Future of Computer Technology and its Implications for the Computer Industry" by Professor Steve Furber. - Peter Y. K. Cheung; Alexandre Yakovlev (Comput. J., 2008)

Custom parallel caching schemes for hardware-accelerated image compression. - Su-Shin Ang; George A. Constantinides; Wayne Luk; Peter Y. K. Cheung (J. Real Time Image Process., 2008)

Affective Level Video Segmentation by Utilizing the Pleasure-Arousal-Dominance Information. - Sutjipto Arifin; Peter Y. K. Cheung (IEEE Trans. Multim., 2008)

Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations. - N. Pete Sedcole; Peter Y. K. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2008)

Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices. - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Outer Loop Pipelining for Application Specific Datapaths in FPGAs. - Kieron Turkington; Turkington A. Constantinides; Kostas Masselos; Peter Y. K. Cheung (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Implementation and Comparison of the 5/3 Lifting 2D Discrete Wavelet Transform Computation Schedules on FPGAs. - Maria E. Angelopoulou; Kostas Masselos; Peter Y. K. Cheung; Yiannis Andreopoulos (J. Signal Process. Syst., 2008)

Parametric Design for Reconfigurable Software-Defined Radio. - Tobias Becker; Wayne Luk; Peter Y. K. Cheung (ARC, 2009)

Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep. - Asma Kahoul; George A. Constantinides; Alastair M. Smith; Peter Y. K. Cheung (ARC, 2009)

A DP-network for optimal dynamic routing in network-on-chip. - Terrence S. T. Mak; Peter Y. K. Cheung; Wayne Luk; Kai-Pui Lam (CODES+ISSS, 2009)

Partition-based exploration for reconfigurable JPEG designs. - Philip G. Potter; Wayne Luk; Peter Y. K. Cheung (DATE, 2009)

Benchmarking Reconfigurable Architectures in the Mobile Domain. - Peter Jamieson; Tobias Becker; Wayne Luk; Peter Y. K. Cheung; Tero Rissa; Teemu Pitkänen (FCCM, 2009)

Compensating for variability in FPGAs by re-mapping and re-placement. - N. Pete Sedcole; Edward A. Stott; Peter Y. K. Cheung (FPL, 2009)

Area estimation and optimisation of FPGA routing fabrics. - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (FPL, 2009)

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. - Alastair M. Smith; George A. Constantinides; Steven J. E. Wilton; Peter Y. K. Cheung (FPT, 2009)

A sensor-based approach to linear blur identification for real-time video enhancement. - Maria E. Angelopoulou; Christos-Savvas Bouganis; Peter Y. K. Cheung (ICIP, 2009)

Throughput Maximization for Wave-pipelined Interconnects using Cascaded Buffers and Transistor Sizing. - Li Wang; Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung (ISCAS, 2009)

High-throughput one-dimensional median and weighted median filters on FPGA. - Suhaib A. Fahmy; Peter Y. K. Cheung; Wayne Luk (IET Comput. Digit. Tech., 2009)

Hardware architectures for eigenvalue computation of real symmetric matrices. - Yang Liu; Christos-Savvas Bouganis; Peter Y. K. Cheung (IET Comput. Digit. Tech., 2009)

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (IET Comput. Digit. Tech., 2009)

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Word-length selection for power minimization via nonlinear optimization. - Jonathan A. Clarke; George A. Constantinides; Peter Y. K. Cheung (ACM Trans. Design Autom. Electr. Syst., 2009)

Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement. - Maria E. Angelopoulou; Christos-Savvas Bouganis; Peter Y. K. Cheung; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2009)

Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs. - Christos-Savvas Bouganis; Sung-Boem Park; George A. Constantinides; Peter Y. K. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2009)

Self-Measurement of Combinatorial Circuit Delays in FPGAs. - Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2009)

Process Variability and Degradation: New Frontier for Reconfigurable. - Peter Y. K. Cheung (ARC, 2010)

Exploration of hardware sharing for image encoders. - Sebastián López; Roberto Sarmiento; Philip G. Potter; Wayne Luk; Peter Y. K. Cheung (DATE, 2010)

Energy-Aware Optimisation for Run-Time Reconfiguration. - Tobias Becker; Wayne Luk; Peter Y. K. Cheung (FCCM, 2010)

Degradation in FPGAs: measurement and modelling. - Edward A. Stott; Justin S. J. Wong; N. Pete Sedcole; Peter Y. K. Cheung (FPGA, 2010)

GPU Versus FPGA for High Productivity Computing. - David Huw Jones; Adam Powell; Christos-Savvas Bouganis; Peter Y. K. Cheung (FPL, 2010)

Degradation Analysis and Mitigation in FPGAs. - Edward A. Stott; Justin S. J. Wong; Peter Y. K. Cheung (FPL, 2010)

A Salient Region Detector for GPU Using a Cellular Automata Architecture. - David Huw Jones; Adam Powell; Christos-Savvas Bouganis; Peter Y. K. Cheung (ICONIP (2), 2010)

Towards anthropomorphic robot Thereminist. - Yan Wu 002; Polake Kuvinichkul; Peter Y. K. Cheung; Yiannis Demiris (ROBIO, 2010)

Fault tolerance and reliability in field-programmable gate arrays. - Edward A. Stott; N. Pete Sedcole; Peter Y. K. Cheung (IET Comput. Digit. Tech., 2010)

Power Characterisation for Fine-Grain Reconfigurable Fabrics. - Tobias Becker; Peter Jamieson; Wayne Luk; Peter Y. K. Cheung; Tero Rissa (Int. J. Reconfigurable Comput., 2010)

Wave-pipelined intra-chip signaling for on-FPGA communications. - Terrence S. T. Mak; N. Pete Sedcole; Peter Y. K. Cheung; Wayne Luk (Integr., 2010)

Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. - Ben Cope; Peter Y. K. Cheung; Wayne Luk; Lee W. Howes (IEEE Trans. Computers, 2010)

FPGA Architecture Optimization Using Geometric Programming. - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. - Peter Jamieson; Tobias Becker; Peter Y. K. Cheung; Wayne Luk; Tero Rissa; Teemu Pitkänen (ACM Trans. Design Autom. Electr. Syst., 2010)

Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods. - Asma Kahoul; Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2010)

An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays. - Alastair M. Smith; George A. Constantinides; Peter Y. K. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2010)

Exploration of Heterogeneous FPGAs for Mapping Linear Projection Designs. - Christos-Savvas Bouganis; Iosifina Pournara; Peter Y. K. Cheung (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only). - Joshua M. Levine; Edward A. Stott; George A. Constantinides; Peter Y. K. Cheung (FPGA, 2011)

Improved delay measurement method in FPGA based on transition probability. - Justin S. J. Wong; Peter Y. K. Cheung (FPGA, 2011)

Improving FPGA Reliability with Wear-Levelling. - Edward A. Stott; Peter Y. K. Cheung (FPL, 2011)

Timing speculation in FPGAs: Probabilistic inference of data dependent failure rates. - Sumanta Chaudhuri; Justin S. J. Wong; Peter Y. K. Cheung (FPT, 2011)

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (Comput. J., 2011)

Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array. - Maria E. Angelopoulou; Christos-Savvas Bouganis; Peter Y. K. Cheung (IET Comput. Digit. Tech., 2011)

A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. - Ben Cope; Peter Y. K. Cheung; Wayne Luk; Lee W. Howes (Trans. High Perform. Embed. Archit. Compil., 2011)

Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. - Terrence S. T. Mak; Peter Y. K. Cheung; Kai-Pui Lam; Wayne Luk (IEEE Trans. Ind. Electron., 2011)

Introduction to special section FPGA 2009. - Peter Y. K. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2011)

Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling. - Joshua M. Levine; Edward A. Stott; George A. Constantinides; Peter Y. K. Cheung (FCCM, 2012)

Adaptive Sequential Monte Carlo approach for real-time applications. - Thomas C. P. Chau; Wayne Luk; Peter Y. K. Cheung; Alison Eele; Jan M. Maciejowski (FPL, 2012)

A two-stage variation-aware placement method for FPGAS exploiting variation maps classification. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (FPL, 2012)

Early performance estimation of image compression methods on soft processors. - Adam Powell; Christos-Savvas Bouganis; Peter Y. K. Cheung (FPL, 2012)

Roberts: reconfigurable platform for benchmarking real-time systems. - Thomas C. P. Chau; Wayne Luk; Peter Y. K. Cheung (SIGARCH Comput. Archit. News, 2012)

Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. - Thomas C. P. Chau; Xinyu Niu; Alison Eele; Wayne Luk; Peter Y. K. Cheung; Jan M. Maciejowski (ARC, 2013)

A variation-adaptive retiming method exploiting reconfigurability. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (FPL, 2013)

SMI: Slack Measurement Insertion for online timing monitoring in FPGAs. - Joshua M. Levine; Edward A. Stott; George A. Constantinides; Peter Y. K. Cheung (FPL, 2013)

Acceleration of real-time Proximity Query for dynamic active constraints. - Thomas C. P. Chau; Ka-Wai Kwok; Gary C. T. Chow; Kuen Hung Tsoi; Kit-Hang Lee; Zion Tse; Peter Y. K. Cheung; Wayne Luk (FPT, 2013)

Datapath fault tolerance for parallel accelerators. - James J. Davis 001; Peter Y. K. Cheung (FPT, 2013)

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (FPT, 2013)

Domain-specific progressive sampling of face images. - Jianxiong Liu; Christos Bouganis; Peter Y. K. Cheung (GlobalSIP, 2013)

Variation and Reliability in FPGAs. - Edward A. Stott; Zhenyu Guan; Joshua M. Levine; Justin S. J. Wong; Peter Y. K. Cheung (IEEE Des. Test, 2013)

High-level power and performance estimation of FPGA-based soft processors and its application to design space exploration. - Adam Powell; Christos-Savvas Bouganis; Peter Y. K. Cheung (J. Syst. Archit., 2013)

Accelerating sequential Monte Carlo method for real-time air traffic management. - Thomas C. P. Chau; James Stanley Targett; Marlon Wijeyasinghe; Wayne Luk; Peter Y. K. Cheung; Benjamin Cope; Alison Eele; Jan M. Maciejowski (SIGARCH Comput. Archit. News, 2013)

Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability. - Justin S. J. Wong; Peter Y. K. Cheung (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Image progressive acquisition for hardware systems. - Jianxiong Liu; Christos-Savvas Bouganis; Peter Y. K. Cheung (DATE, 2014)

SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. - Thomas C. P. Chau; Maciej Kurek; James Stanley Targett; Jake Humphrey; Georgios Skouroupathis; Alison Eele; Jan M. Maciejowski; Benjamin Cope; Kathryn Cobden; Philip Heng Wai Leong; Peter Y. K. Cheung; Wayne Luk (FCCM, 2014)

Reducing Overheads for Fault-Tolerant Datapaths with Dynamic Partial Reconfiguration. - James J. Davis 001; Peter Y. K. Cheung (FCCM, 2014)

Timing Fault Detection in FPGA-Based Circuits. - Edward A. Stott; Joshua M. Levine; Peter Y. K. Cheung; Nachiket Kapre (FCCM, 2014)

Dynamic voltage & frequency scaling with online slack measurement. - Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung (FPGA, 2014)

Achieving low-overhead fault tolerance for parallel accelerators with dynamic partial reconfiguration. - James J. Davis 001; Peter Y. K. Cheung (FPL, 2014)

Kernel-based Adaptive Image Sampling. - Jianxiong Liu; Christos Bouganis; Peter Y. K. Cheung (VISAPP (1), 2014)

Classification on variation maps: a new placement strategy to alleviate process variation on FPGA. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (IEICE Electron. Express, 2014)

Mitigation of process variation effect in FPGAs with partial rerouting method. - Zhenyu Guan; Justin S. J. Wong; Sumanta Chaudhuri; George A. Constantinides; Peter Y. K. Cheung (IEICE Electron. Express, 2014)

Preface. - Peter Y. K. Cheung; Wayne Luk; Cristina Silvano (FPL, 2015)

An efficient architecture for zero overhead data en-/decryption using reconfigurable cryptographic engine. - Bony H. K. Chen; Paul Y. S. Cheung; Peter Y. K. Cheung; Yu-Kwong Kwok (FPT, 2015)

G-DMA: improving memory access performance for hardware accelerated sparse graph computation. - Andrew Bean; Nachiket Kapre; Peter Y. K. Cheung (ReConFig, 2015)

Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. - Thomas C. P. Chau; Xinyu Niu; Alison Eele; Jan M. Maciejowski; Peter Y. K. Cheung; Wayne Luk (ACM Trans. Reconfigurable Technol. Syst., 2015)

Reduced-precision Algorithm-based Fault Tolerance for FPGA-implemented Accelerators. - James J. Davis 001; Peter Y. K. Cheung (ARC, 2016)

KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs. - Eddie Hung; James J. Davis 001; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (FCCM, 2016)

Increasing Network Size and Training Throughput of FPGA Restricted Boltzmann Machines Using Dropout. - Jiang Su; David B. Thomas; Peter Y. K. Cheung (FCCM, 2016)

Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only). - James J. Davis 001; Eddie Hung; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (FPGA, 2016)

Neural Network Based Reinforcement Learning Acceleration on FPGA Platforms. - Jiang Su; Jianxiong Liu; David B. Thomas; Peter Y. K. Cheung (SIGARCH Comput. Archit. News, 2016)

STRIPE: Signal selection for runtime power estimation. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (FPL, 2017)

KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (IEEE Des. Test, 2017)

Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic. - Jiang Su; Nicholas J. Fraser; Giulio Gambardella; Michaela Blott; Gianluca Durelli; David B. Thomas; Philip Heng Wai Leong; Peter Y. K. Cheung (ARC, 2018)

Redundancy-Reduced MobileNet Acceleration on Reconfigurable Logic for ImageNet Classification. - Jiang Su; Julian Faraone; Junyi Liu; Yiren Zhao; David B. Thomas; Philip Heng Wai Leong; Peter Y. K. Cheung (ARC, 2018)

Hardware Compilation of Deep Neural Networks: An Overview. - Ruizhe Zhao; Shuanglong Liu; Ho-Cheung Ng; Erwei Wang; James J. Davis 001; Xinyu Niu; Xiwei Wang; Huifeng Shi; George A. Constantinides; Peter Y. K. Cheung; Wayne Luk (ASAP, 2018)

A PYNQ-Based Framework for Rapid CNN Prototyping. - Erwei Wang; James J. Davis 001; Peter Y. K. Cheung (FCCM, 2018)

Accelerating Top-k ListNet Training for Ranking Using FPGA. - Qiang Li; Shane T. Fleming; David B. Thomas; Peter Y. K. Cheung (FPT, 2018)

KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications. - James J. Davis 001; Joshua M. Levine; Edward A. Stott; Eddie Hung; Peter Y. K. Cheung; George A. Constantinides (IWOCL, 2018)

CypherDB: A Novel Architecture for Outsourcing Secure Database Processing. - Bony H. K. Chen; Paul Y. S. Cheung; Peter Y. K. Cheung; Yu-Kwong Kwok (IEEE Trans. Cloud Comput., 2018)

KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs. - James J. Davis 001; Eddie Hung; Joshua M. Levine; Edward A. Stott; Peter Y. K. Cheung; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2018)

LUTNet: Rethinking Inference in FPGA Soft Logic. - Erwei Wang; James J. Davis 001; Peter Y. K. Cheung; George A. Constantinides (FCCM, 2019)

Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. - Qiang Li; Erwei Wang; Shane T. Fleming; David B. Thomas; Peter Y. K. Cheung (FPL, 2019)

Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. - Yiren Zhao; Xitong Gao; Xuan Guo; Junyi Liu; Erwei Wang; Robert D. Mullins; Peter Y. K. Cheung; George A. Constantinides; Cheng-Zhong Xu 001 (FPT, 2019)

Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. - Erwei Wang; James J. Davis 001; Ruizhe Zhao; Ho-Cheung Ng; Xinyu Niu; Wayne Luk; Peter Y. K. Cheung; George A. Constantinides (ACM Comput. Surv., 2019)

Context-based image acquisition from memory in digital systems. - Jianxiong Liu; Christos Bouganis; Peter Y. K. Cheung (J. Real Time Image Process., 2019)

On Fast Multi-Shot Epidemic Interventions for Post Lock-Down Mitigation: Implications for Simple Covid-19 Models. - Michelangelo Bin; Peter Y. K. Cheung; Emanuele Crisostomi; Pietro Ferraro; Connor Myant; Thomas Parisini; Robert Shorten (CoRR, 2020)

LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference. - Erwei Wang; James J. Davis 001; Peter Y. K. Cheung; George A. Constantinides (IEEE Trans. Computers, 2020)

Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. - Zhiqiang Que; Erwei Wang; Umar Marikar; Eric A. Moreno; Jennifer Ngadiuba; Hamza Javed; Bartlomiej Borzyszkowski; Thea Aarrestad; Vladimir Loncar; Sioni Summers; Maurizio Pierini; Peter Y. K. Cheung; et al. (ASAP, 2021)

Enabling Binary Neural Network Training on the Edge. - Erwei Wang; James J. Davis 001; Daniele Moro; Piotr Zielinski; Claudionor Coelho; Satrajit Chatterjee; Peter Y. K. Cheung; George A. Constantinides (CoRR, 2021)

Post-lockdown abatement of COVID-19 by fast periodic switching. - Michelangelo Bin; Peter Y. K. Cheung; Emanuele Crisostomi; Pietro Ferraro; Hugo Lhachemi; Roderick Murray-Smith; Connor Myant; Thomas Parisini; Robert Shorten; Sebastian Stein 003; Lewi Stone (PLoS Comput. Biol., 2021)

Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference. - Erwei Wang; James J. Davis 001; Georgios-Ilias Stavrou; Peter Y. K. Cheung; George A. Constantinides; Mohamed S. Abdelfattah (FPGA, 2022)

Enabling Binary Neural Network Training on the Edge. - Erwei Wang; James J. Davis 001; Daniele Moro; Piotr Zielinski; Jia Jie Lim; Claudionor Coelho; Satrajit Chatterjee; Peter Y. K. Cheung; George A. Constantinides (ACM Trans. Embed. Comput. Syst., 2023)

Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks. - Erwei Wang; Marie Auffret; Georgios-Ilias Stavrou; Peter Y. K. Cheung; George A. Constantinides; Mohamed S. Abdelfattah; James J. Davis 001 (ACM Trans. Reconfigurable Technol. Syst., 2023)

Verification and Fault Injection Platform Based on MTB Stimulus Generation Method for L2 Deep Market Quote Decoder. - Le Yu; Zhiheng Liang; Yaqi Li; Shiwei Zhang; Yiren Zhao; Peter Y. K. Cheung (IEEE Access, 2024)