System Design with Genetic Algorithms. - Christine Bauer 002; Peter Zipf; Hans Wojtkowiak (FPL, 2000)

Integration und Fehlertoleranz im Codesign. - Christine Bauer 002; Peter Zipf; Hans Wojtkowiak (MBMV, 2000)

Fly - A Modifiable Hardware Compiler. - Chun Hok Ho; Philip Heng Wai Leong; Kuen Hung Tsoi; Ralf Ludewig; Peter Zipf; Alberto García Ortiz; Manfred Glesner (FPL, 2002)

A Framework for Teaching (Re)Configurable Architectures in Student Projects. - Thilo Pionteck; Peter Zipf; Lukusa D. Kabulepa; Manfred Glesner (FPL, 2002)

Handling FPGA Faults and Configuration Sequencing Using a Hardware Extension. - Peter Zipf; Manfred Glesner; Christine Bauer 002; Hans Wojtkowiak (FPL, 2002)

A granularity-based classification model for systems-on-a-chip. - Stephan Bingemer; Peter Zipf; Manfred Glesner (FPGA, 2003)

Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. - Tudor Murgan; Mihail Petrov; Alberto García Ortiz; Ralf Ludewig; Peter Zipf; Thomas Hollstein; Manfred Glesner; Bernard Ölkrug; Jörg Brakensiek (FPL, 2003)

Arbitrary function approximation in HDLs with application to the N-body problem. - Chun Hok Ho; Kuen Hung Tsoi; Jackson H. C. Yeung; Yuet Ming Lam; Kin-Hong Lee; Philip Heng Wai Leong; Ralf Ludewig; Peter Zipf; Alberto García Ortiz; Manfred Glesner (FPT, 2003)

An Integrated Model Bridging the Gap between Technology and Economy. - Stephan Bingemer; Peter Zipf; Manfred Glesner (VLSI-SOC, 2003)

A hierarchical generic approach for on-chip communication, testing and debugging of SoCs. - Thomas Hollstein; Ralf Ludewig; Christoph Mager; Peter Zipf; Manfred Glesner (VLSI-SOC, 2003)

An Adaptive Trace-Back Solution for State-Parallel Viterbi Decoders. - Mihail Petrov; Abdulfattah Mohammad Obeid; Tudor Murgan; Peter Zipf; Jörg Brakensiek; Bernard Ölkrug; Manfred Glesner (VLSI-SOC, 2003)

Reconfigurable platforms for ubiquitous computing. - Manfred Glesner; Thomas Hollstein; Leandro Soares Indrusiak; Peter Zipf; Thilo Pionteck; Mihail Petrov; Heiko Zimmer; Tudor Murgan (Conf. Computing Frontiers, 2004)

Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. - Tudor Murgan; Mihail Petrov; Mateusz Majer; Peter Zipf; Manfred Glesner; Ulrich Heinkel; Jörg Pleickhardt; Bernd Bleisteiner (Conf. Computing Frontiers, 2004)

IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. - Ralf Ludewig; Oliver Soffke; Peter Zipf; Manfred Glesner; Kong-Pang Pun; Kuen Hung Tsoi; Kin-Hong Lee; Philip Heng Wai Leong (FPL, 2004)

The XPP Architecture and Its Co-simulation Within the Simulink Environment. - Mihail Petrov; Tudor Murgan; Frank May; Martin Vorbach; Peter Zipf; Manfred Glesner (FPL, 2004)

Dynamic power optimization of the trace-back process for the Viterbi algorithm. - Mihail Petrov; Tudor Murgan; Abdulfattah Mohammad Obeid; Cristian Chitu; Peter Zipf; Jörg Brakensiek; Manfred Glesner (ISCAS (2), 2004)

A Configurable Pipelined State Machine as a Hybrid ASIC and Configurable Architecture. - Peter Zipf; Claude Stötzler; Manfred Glesner (ISVLSI, 2004)

Flexible Overhead Processing Architectures for G.709 Optical Transport Networks. - Tudor Murgan; Mihail Petrov; Mateusz Majer; Peter Zipf; Manfred Glesner; Ulrich Heinkel (MBMV, 2004)

An Asynchronous Switch Implmentation for Systems-on-a-Chip. - Peter Zipf; Heiko Hinkelmann; Adeel Ashraf; Thomas Hollstein; Manfred Glesner (MBMV, 2004)

A switch architecture and signal synchronization for GALS system-on-chips. - Peter Zipf; Heiko Hinkelmann; Adeel Ashraf; Manfred Glesner (SBCCI, 2004)

CONAN - A Design Exploration Framework for Reliable Nano-Electronics. - Sorin Cotofana; Alexandre Schmid; Yusuf Leblebici; Adrian M. Ionescu; Oliver Soffke; Peter Zipf; Manfred Glesner; Antonio Rubio 001 (ASAP, 2005)

Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. - Peter Zipf; Oliver Soffke; Andre Schumacher; Radu Dogaru; Manfred Glesner (FPL, 2005)

A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. - Peter Zipf; Oliver Soffke; Andre Schumacher; Clemens Schlachta; Radu Dogaru; Manfred Glesner (FPL, 2005)

Eine weiterentwickelte quasi-statische adiabatische Logikfamilie. - Clemens Schlachta; Oliver Soffke; Peter Zipf; Manfred Glesner (GI Jahrestagung (1), 2005)

Abstrakte Modellierung der Eigenschaften von nanoelektronischen CNT-Elementen in SystemC. - Peter Zipf; Oliver Soffke; Michael Velten; Manfred Glesner (GI Jahrestagung (1), 2005)

Functional modeling techniques for a wireless LAN OFDM transceiver. - A. Petrov; Tudor Murgan; Peter Zipf; Manfred Glesner (ISCAS (4), 2005)

Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. - Tudor Murgan; Abdulfattah Mohammad Obeid; Andre Guntoro; Peter Zipf; Manfred Glesner; Ulrich Heinkel (ReCoSoC, 2005)

Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. - Peter Zipf; Claude Stötzler; Manfred Glesner (ReCoSoC, 2005)

Reconfigurable Embedded Systems: An Application-Oriented Perspective on Architectures and Design Techniques. - Manfred Glesner; Heiko Hinkelmann; Thomas Hollstein; Leandro Soares Indrusiak; Tudor Murgan; Abdulfattah Mohammad Obeid; Mihail Petrov; Thilo Pionteck; Peter Zipf (SAMOS, 2005)

Design Concepts for a Dynamically ReconfigurableWireless Sensor Node. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner (AHS, 2006)

Implementation of Realtime and Highspeed Phase Detector on FPGA. - Andre Guntoro; Peter Zipf; Oliver Soffke; Harald Klingbeil; Martin Kumm; Manfred Glesner (ARC, 2006)

A metric for the energy-efficiency of dynamically reconfigurable systems. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner (ARCS Workshops, 2006)

Towards an Automated Design of Application-specific Reconfigurable Logic. - Peter Zipf; Manfred Glesner (Dynamically Reconfigurable Architectures, 2006)

A signal theory based approach to the statistical analysis of combinatorial nanoelectronic circuits. - Oliver Soffke; Peter Zipf; Tudor Murgan; Manfred Glesner (DATE, 2006)

Multitasking Support for Dynamically Reconfig Urable Systems. - Heiko Hinkelmann; Andreas Gunberg; Peter Zipf; Leandro Soares Indrusiak; Manfred Glesner (FPL, 2006)

Eine Scheduling Heuristik zur Minimierung der Verlustleistung. - Peter Zipf; Volker Hampel; Manfred Glesner; Thilo Pionteck (MBMV, 2006)

A Concept for a Profile-based Dynamic Reconfiguration Mechanism. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner (ReCoSoC, 2006)

A Power Estimation Model for an FPGA-based Softcore Processor. - Peter Zipf; Heiko Hinkelmann; Lei Deng; Manfred Glesner; Holger Blume; Tobias G. Noll (FPL, 2007)

A Domain-Specific Dynamically Reconfigurable Hardware Platform for Wireless Sensor Networks. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner (FPT, 2007)

Ein Beitrag zur automatischen Erzeugung dynamisch rekonfigurierbarer Hardwarestrukturen. - Peter Zipf; Yang Qiao; Manfred Glesner (MBMV, 2007)

On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. - Heiko Hinkelmann; Tudor Murgan; Guifang Liu; Peter Zipf; Manfred Glesner (ReCoSoC, 2007)

A Customizable LEON2-Based VLIW Processor. - Peter Zipf; Heiko Hinkelmann; Felix Missel; Manfred Glesner (ReCoSoC, 2007)

Dynamically Reconfigurable Computing for Wireless Communication Systems (Dynamisch rekonfigurierbares Rechnen für Mobilfunksysteme). - Heiko Hinkelmann; Peter Zipf; Manfred Glesner; Thilo Pionteck (it Inf. Technol., 2007)

Coarse-grained reconfiguration. - Sven Eisenhardt; Thomas Schweizer; Julio A. de Oliveira Filho; Tobias Oppold; Wolfgang Rosenstiel; Alexander Thomas; Jürgen Becker 001; Frank Hannig; Dmitrij Kissler; Hritam Dutta; Jürgen Teich; Heiko Hinkelmann; et al. (FPL, 2008)

Application-specific reconfigurable processors. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner; Matthias Alles; Timo Vogt; Norbert Wehn; Götz Kappen; Tobias G. Noll (FPL, 2008)

A scalable reconfiguration mechanism for fast dynamic reconfiguration. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner (FPT, 2008)

An area-efficient FPGA realisation of a codebook-based image compression method. - Peter Zipf; Heiko Hinkelmann; Hui Shao; Radu Dogaru; Manfred Glesner (FPT, 2008)

Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II. - Christopher Spies; Peter Zipf; Manfred Glesner; Harald Klingbeil (IEEE International Workshop on Rapid System Prototyping, 2008)

Applying Dynamic Reconfiguration for Fault Tolerance in Fine-Grained Logic Arrays. - Peter Zipf (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Design and evaluation of an energy-efficient dynamically reconfigurable architecture for wireless sensor nodes. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner (FPL, 2009)

An integrated tool flow to realize runtime-reconfigurable applications on a new class of partial multi-context FPGAs. - Markus Rullmann; Renate Merker; Heiko Hinkelmann; Peter Zipf; Manfred Glesner (FPL, 2009)

Towards a unique FPGA-based identification circuit using process variations. - Haile Yu; Philip Heng Wai Leong; Heiko Hinkelmann; Leandro Möller; Manfred Glesner; Peter Zipf (FPL, 2009)

Generation of Synthetic Floating-Point benchmark circuits. - Thomas C. P. Chau; S. Man Ho Ho; Philip Heng Wai Leong; Peter Zipf; Manfred Glesner (IPDPS, 2009)

Selected Papers from ReCoSoC 2008. - Michael Hübner 001; Juan Manuel Moreno; Gilles Sassatelli; Peter Zipf (Int. J. Reconfigurable Comput., 2009)

A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips. - Peter Zipf; Gilles Sassatelli; Nurten Utlu; Nicolas Saint-Jean; Pascal Benoit; Manfred Glesner (Int. J. Reconfigurable Comput., 2009)

On the design of reconfigurable multipliers for integer and Galois field multiplication. - Heiko Hinkelmann; Peter Zipf; Jia Li; Guifang Liu; Manfred Glesner (Microprocess. Microsystems, 2009)

Dynamically Reconfigurable Systems for Wireless Sensor Networks. - Heiko Hinkelmann; Peter Zipf; Manfred Glesner (Dynamically Reconfigurable Systems, 2010)

An FPGA-Based Linear All-Digital Phase-Locked Loop. - Martin Kumm; Harald Klingbeil; Peter Zipf (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

High speed low complexity FPGA-based FIR filters using pipelined adder graphs. - Martin Kumm; Peter Zipf (FPT, 2011)

Reduced complexity single and multiple constant multiplication in floating point precision. - Martin Kumm; Katharina Liebisch; Peter Zipf (FPL, 2012)

Area estimation of look-up table based fixed-point computations on the example of a real-time high dynamic range imaging system. - Michael Kunz; Martin Kumm; Martin Heide; Peter Zipf (FPL, 2012)

Hybrid multiple constant multiplication for FPGAs. - Martin Kumm; Peter Zipf (ICECS, 2012)

Pipelined adder graph optimization for high speed multiple constant multiplication. - Martin Kumm; Peter Zipf; Mathias Faust; Chip-Hong Chang (ISCAS, 2012)

Multiple constant multiplication with ternary adders. - Martin Kumm; Martin Hardieck; Jens Willkomm; Peter Zipf; Uwe Meyer-Baese (FPL, 2013)

Partial LUT size analysis in distributed arithmetic FIR Filters on FPGAs. - Martin Kumm; Konrad Möller; Peter Zipf (ISCAS, 2013)

Reconfigurable FIR filter using distributed arithmetic on FPGAs. - Martin Kumm; Konrad Möller; Peter Zipf (ISCAS, 2013)

Dynamically reconfigurable FIR filter architectures with fast reconfiguration. - Martin Kumm; Konrad Möller; Peter Zipf (ReCoSoC, 2013)

FIR filter optimization for video processing on FPGAs. - Martin Kumm; Diana Fanghänel; Konrad Möller; Peter Zipf; Uwe Meyer-Baese (EURASIP J. Adv. Signal Process., 2013)

Pipelined compressor tree optimization using integer linear programming. - Martin Kumm; Peter Zipf (FPL, 2014)

An FPGA-optimized architecture of horn and schunck optical flow algorithm for real-time applications. - Michael Kunz; Alexander Ostrowski; Peter Zipf (FPL, 2014)

Pipelined reconfigurable multiplication with constants on FPGAs. - Konrad Möller; Martin Kumm; Marco Kleinlein; Peter Zipf (FPL, 2014)

Efficient High Speed Compression Trees on Xilinx FPGAs. - Martin Kumm; Peter Zipf (MBMV, 2014)

Dynamically Reconfigurable Constant Multiplication on FPGAs. - Konrad Möller; Martin Kumm; Björn Barschtipan; Peter Zipf (MBMV, 2014)

An Efficient Softcore Multiplier Architecture for Xilinx FPGAs. - Martin Kumm; Shahid Abbas; Peter Zipf (ARITH, 2015)

Efficient structural adder pipelining in transposed form FIR filters. - Mathias Faust; Martin Kumm; Chip-Hong Chang; Peter Zipf (DSP, 2015)

Model-based Hardware Design for FPGAs using Folding Transformations based on Subcircuits. - Konrad Möller; Martin Kumm; Charles-Frederic Müller; Peter Zipf (CoRR, 2015)

Efficient sum of absolute difference computation on FPGAs. - Martin Kumm; Marco Kleinlein; Peter Zipf (FPL, 2016)

Comment on "High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs". - Martin Kumm; Peter Zipf (Int. J. Reconfigurable Comput., 2016)

Resource Optimal Design of Large Multipliers for FPGAs. - Martin Kumm; Johannes Kappauf; Matei Istoan; Peter Zipf (ARITH, 2017)

Model-based hardware design based on compatible sets of isomorphic subgraphs. - Patrick Sittel; Konrad Möller; Martin Kumm; Peter Zipf; Bogdan Pasca 001; Mark Jervis (FPT, 2017)

High-Level Synthesis for Model-Based Design with Automatic Folding including Combined Common Subcircuits. - Patrick Sittel; Martin Kumm; Konrad Möller; Martin Hardieck; Peter Zipf (MBMV, 2017)

Optimization of Constant Matrix Multiplication with Low Power and High Throughput. - Martin Kumm; Martin Hardieck; Peter Zipf (IEEE Trans. Computers, 2017)

Reconfigurable Constant Multiplication for FPGAs. - Konrad Möller; Martin Kumm; Marco Kleinlein; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Karatsuba with Rectangular Multipliers for FPGAs. - Martin Kumm; Oscar Gustafsson; Florent de Dinechin; Johannes Kappauf; Peter Zipf (ARITH, 2018)

ILP-Based Modulo Scheduling and Binding for Register Minimization. - Patrick Sittel; Martin Kumm; Julian Oppermann; Konrad Möller; Peter Zipf; Andreas Koch 001 (FPL, 2018)

Constant Matrix Multiplication with Ternary Adders. - Martin Hardieck; Martin Kumm; Patrick Sittel; Peter Zipf (ICECS, 2018)

ScaLP: A Light-Weighted (MI)LP-Library. - Patrick Sittel; Thomas Schönwälder; Martin Kumm; Peter Zipf (MBMV, 2018)

Optimal Shift Reassignment in Reconfigurable Constant Multiplication Circuits. - Konrad Möller; Martin Kumm; Mario Garrido; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Optimal Single Constant Multiplication Using Ternary Adders. - Martin Kumm; Oscar Gustafsson; Mario Garrido; Peter Zipf (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Efficient Error-Tolerant Quantized Neural Network Accelerators. - Giulio Gambardella; Johannes Kappauf; Michaela Blott; Christoph Doehring; Martin Kumm; Peter Zipf; Kees A. Vissers (DFT, 2019)

Reconfigurable Convolutional Kernels for Neural Networks on FPGAs. - Martin Hardieck; Martin Kumm; Konrad Möller; Peter Zipf (FPGA, 2019)

Isomorphic Subgraph-based Problem Reduction for Resource Minimal Modulo Scheduling. - Patrick Sittel; Nicolai Fiege; Martin Kumm; Peter Zipf (ReConFig, 2019)

Unrolling Ternary Neural Networks. - Stephen Tridgell; Martin Kumm; Martin Hardieck; David Boland; Duncan J. M. Moss; Peter Zipf; Philip H. W. Leong (ACM Trans. Reconfigurable Technol. Syst., 2019)

Modulo Scheduling with Rational Initiation Intervals in Custom Hardware Design. - Patrick Sittel; John Wickerson; Martin Kumm; Peter Zipf (ASP-DAC, 2020)

AddNet: Deep Neural Networks Using FPGA-Optimized Multipliers. - Julian Faraone; Martin Kumm; Martin Hardieck; Peter Zipf; Xueyuan Liu 002; David Boland; Philip H. W. Leong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Towards Highly Automated Machine-Learning-Empowered Monitoring of Motor Test Stands. - Diego Botache; Florian Bethke; Martin Hardieck; Maarten Bieshaar; Ludwig Brabetz; Mohamed Ayeb; Peter Zipf; Bernhard Sick (ACSOS, 2021)

Improving Energy Efficiency in Loop Pipelining by Rational-II Modulo Scheduling. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FCCM, 2022)

Optimal Binding and Port Assignment for Loop Pipelining in High-Level Synthesis. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FPL, 2022)

Speeding Up Optimal Modulo Scheduling with Rational Initiation Intervals. - Nicolai Fiege; Patrick Sittel; Peter Zipf (FPL, 2022)

Optimal and Heuristic Approaches to Modulo Scheduling With Rational Initiation Intervals in Hardware Synthesis. - Patrick Sittel; Nicolai Fiege; John Wickerson; Peter Zipf (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

More AddNet: A deeper insight into DNNs using FPGA-optimized multipliers. - Martin Hardieck; Tobias Habermann; Fabian Wagner; Michael Mecik; Martin Kumm; Peter Zipf (ISCAS, 2023)

BLOOP: Boolean Satisfiability-based Optimized Loop Pipelining. - Nicolai Fiege; Peter Zipf (ACM Trans. Reconfigurable Technol. Syst., 2023)

Bit-Level Optimized Constant Multiplication Using Boolean Satisfiability. - Nicolai Fiege; Martin Kumm; Peter Zipf (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Fantastic Circuits and Where to Find Them - A Holistic ILP Formulation for Model-Based Hardware Design. - Nicolai Fiege; Peter Zipf (ACM Trans. Reconfigurable Technol. Syst., 2025)