On the Use of Mutations in Boolean Minimization. - Petr Fiser; Jan Hlavicka (DSD, 2001)

Minimization and Partitioning Method Reducing Input Sets. - Jan Hlavicka; Petr Fiser (DELTA, 2002)

FC-Min: A Fast Multi-Output Boolean Minimizer. - Petr Fiser; Jan Hlavicka; Hana Kubátová (DSD, 2003)

BOOM - A Heuristic Boolean Minimizer. - Jan Hlavicka; Petr Fiser (Comput. Artif. Intell., 2003)

Boolean Minimizer FC-Min: Coverage Finding Process. - Petr Fiser; Hana Kubátová (DSD, 2004)

Survey of the Algorithms in the Column-Matching BIST Method. - Petr Fiser; Hana Kubátová (IOLTS, 2004)

Multiple-Vector Column-Matching BIST Design Method. - Petr Fiser; Hana Kubátová (DDECS, 2006)

Flexible Two-Level Boolean Minimizer BOOM-II and Its Applications. - Petr Fiser; Hana Kubátová (DSD, 2006)

Fault Tolerant System Design Method Based on Self-Checking Circuits. - Pavel Kubalík; Petr Fiser; Hana Kubátová (IOLTS, 2006)

Pseudo-Random Pattern Generator Design for Column-Matching BIST. - Petr Fiser (DSD, 2007)

Fast Boolean Minimizer for Completely Specified Functions. - Petr Fiser; Pemysl Rucký; Irena Vanová (DDECS, 2008)

An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. - Petr Fiser; Pavel Kubalík; Hana Kubátová (DSD, 2008)

Column-matching based mixed-mode test pattern generator design technique for BIST. - Petr Fiser; Hana Kubátová (Microprocess. Microsystems, 2008)

Asynchronous two-level logic of reduced cost. - Igor Lemberski; Petr Fiser (DDECS, 2009)

A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms. - Petr Fiser; David Toman 002 (DSD, 2009)

The Case for a Balanced Decomposition Process. - Jan Schmidt; Petr Fiser (DSD, 2009)

On logic synthesis of conventionally hard to synthesize circuits using genetic programming. - Petr Fiser; Jan Schmidt; Zdenek Vasícek; Lukás Sekanina (DDECS, 2010)

Test Patterns Compression Technique Based on a Dedicated SAT-Based ATPG. - Jiri Balcarek; Petr Fiser; Jan Schmidt (DSD, 2010)

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints. - Igor Lemberski; Petr Fiser (DSD, 2010)

Improving the iterative power of resynthesis. - Petr Fiser; Jan Schmidt (DDECS, 2012)

The Influence of Implementation Technology on Dependability Parameters. - Jan Schmidt; Petr Fiser; Jiri Balcarek (DSD, 2012)

Simulation and SAT Based ATPG for Compressed Test Generation. - Jiri Balcarek; Petr Fiser; Jan Schmidt (DSD, 2013)

Techniques for SAT-based constrained test pattern generation. - Jiri Balcarek; Petr Fiser; Jan Schmidt (Microprocess. Microsystems, 2013)

The influence of implementation type on dependability parameters. - Jan Schmidt; Petr Fiser; Jiri Balcarek (Microprocess. Microsystems, 2013)

Sources of bias in EDA tools and its influence. - Petr Fiser; Jan Schmidt; Jiri Balcarek (DDECS, 2014)

PBO-Based Test Compression. - Jiri Balcarek; Petr Fiser; Jan Schmidt (DSD, 2014)

On Robustness of EDA Tools. - Jan Schmidt; Petr Fiser; Jiri Balcarek (DSD, 2014)

Asynchronous sum-of-products logic minimization and orthogonalization. - Igor Lemberski; Petr Fiser; Ruslan Suleimanov (Int. J. Circuit Theory Appl., 2014)

Dual-rail asynchronous logic multi-level implementation. - Igor Lemberski; Petr Fiser (Integr., 2014)

On don't cares in test compression. - Jirí Balcárek; Petr Fiser; Jan Schmidt (Microprocess. Microsystems, 2014)

Novel C-Element Based Error Detection and Correction Method Combining Time and Area Redundancy. - Jan Belohoubek; Petr Fiser; Jan Schmidt (DSD, 2015)

A rule-based approach for minimizing power dissipation of digital circuits. - Subrata Das; Parthasarathi Dasgupta; Petr Fiser; Sudip Ghosh 001; Debesh Kumar Das (DDECS, 2016)

A new user-friendly ATPG platform for digital circuits. - Marek Lipovský; Ján Svarc; Elena Gramatová; Petr Fiser (DDECS, 2016)

A new method for path criticality calculation. - Róbert Tamási; Miroslav Siebert; Elena Gramatová; Petr Fiser (DDECS, 2016)

Error Correction Method Based on the Short-Duration Offline Test. - Jan Belohoubek; Petr Fiser; Jan Schmidt (DSD, 2016)

Are XORs in logic synthesis really necessary? - Ivo Hálecek; Petr Fiser; Jan Schmidt (DDECS, 2017)

SAT-Based Generation of Optimum Function Implementations with XOR Gates. - Petr Fiser; Ivo Hálecek; Jan Schmidt (DSD, 2017)

SAT-Based ATPG for Zero-Aliasing Compaction. - Robert Hülle; Petr Fiser; Jan Schmidt (DSD, 2017)

Error masking method based on the short-duration offline test. - Jan Belohoubek; Petr Fiser; Jan Schmidt (Microprocess. Microsystems, 2017)

Synthesis of Finite State Machines on Memristor Crossbars. - Umberto Ferrandino; Marcello Traiola; Mario Barbareschi; Antonino Mazzeo; Petr Fiser; Alberto Bosio (DDECS, 2018)

Optimum polymorphic circuits synthesis method. - Petr Fiser; Václav Simek (DTIS, 2018)

ZATPG: SAT-based test patterns generator with zero-aliasing in temporal compaction. - Robert Hülle; Petr Fiser; Jan Schmidt (Microprocess. Microsystems, 2018)

Towards AND/XOR balanced synthesis: Logic circuits rewriting with XOR. - Ivo Hálecek; Petr Fiser; Jan Schmidt (Microelectron. Reliab., 2018)

Using Voters May Lead to Secret Leakage. - Jan Belohoubek; Petr Fiser; Jan Schmidt (DDECS, 2019)

CMOS Illumination Discloses Processed Data. - Jan Belohoubek; Petr Fiser; Jan Schmidt (DSD, 2019)

SAT-Based Generation of Optimum Circuits with Polymorphic Behavior Support. - Petr Fiser; Ivo Hálecek; Jan Schmidt; Václav Simek (J. Circuits Syst. Comput., 2019)

Standard Cell Tuning Enables Data-Independent Static Power Consumption. - Jan Belohoubek; Petr Fiser; Jan Schmidt (DDECS, 2020)

Evaluation of the SEU Faults Coverage of a Simple Fault Model for Application-Oriented FPGA Testing. - Jaroslav Borecký; Robert Hülle; Petr Fiser (DSD, 2020)

Special issue on DSD 2018. - Martin Novotný; Petr Fiser (Microprocess. Microsystems, 2020)

Emerging Technologies: Challenges and Opportunities for Logic Synthesis. - Alberto Bosio; Mayeul Cantan; Cédric Marchand 002; Ian O'Connor; Petr Fiser; Arnaud Poittevin; Marcello Traiola (DDECS, 2021)

Minimization of Switching Activity of Graphene Based Circuits. - Subrata Das; Petr Fiser; Soumya Pandit; Debesh Kumar Das (VLSID, 2021)

A Design Space Exploration Framework for Memristor-Based Crossbar Architecture. - Mario Barbareschi; Alberto Bosio; Ian O'Connor; Petr Fiser; Marcello Traiola (DDECS, 2022)

Reducing Output Response Aliasing Using Boolean Optimization Techniques. - Robert Hülle; Petr Fiser; Jan Schmidt (DDECS, 2023)

On the Influence of the Laser Illumination on the Logic Cells Current Consumption : First measurement results. - Dmytro Petryk; Zoya Dyka; Milos Krstic; Jan Belohoubek; Petr Fiser; Frantisek Steiner; Tomás Blecha; Peter Langendörfer; Ievgen Kabin (ICECS, 2023)

Switching Activity Reduction in Graphene PN Junction Circuits using Circuit Re-structuring. - Subrata Das; Arighna Deb; Petr Fiser (ISDCS, 2023)

A Comparison of Logic Extraction Methods in Hardware-Translated Neural Networks. - Jan Schmidt; Petr Fiser; Miroslav Skrbek (DDECS, 2024)

Adaptive Input Normalization for Quantized Neural Networks. - Jan Schmidt; Petr Fiser; Miroslav Skrbek (DDECS, 2024)

Design Objectives for Synthesis of Graphene PN Junction Circuits Based on Two-Level Representation. - Subrata Das; Arighna Deb; Petr Fiser; Debesh Kumar Das (DSD, 2024)

On the Influence of the Laser Illumination on the Logic Cells Current Consumption. - Dmytro Petryk; Zoya Dyka; Milos Krstic; Jan Belohoubek; Petr Fiser; Frantisek Steiner; Tomás Blecha; Peter Langendörfer; Ievgen Kabin (CoRR, 2024)

Structural bias in synthesis of sparsely-specified functions. - Petr Fiser; Jan Schmidt (it Inf. Technol., 2024)

Controllability-Based Circuit Similarity Estimation. - Michal Zácek; Petr Fiser (DDECS, 2025)