Incorporating Energy and Throughput Awareness in Design Space Exploration and Run-Time Mapping for Heterogeneous MPSoCs. - Pham Nam Khanh; Amit Kumar Singh 002; Akash Kumar 001; Khin Mi Mi Aung (DSD, 2013)

Design Space Exploration to Accelerate Nelder-Mead Algorithm Using FPGA. - Pham Nam Khanh; Amit Kumar Singh 002; Akash Kumar 001; Khin Mi Mi Aung (FCCM, 2014)

Leakage and performance aware resource management for 2D dynamically reconfigurable FPGA architectures. - Siqi Wang; Pham Nam Khanh; Amit Kumar Singh 002; Akash Kumar 001 (FPL, 2014)

A multi-stage leakage aware resource management technique for reconfigurable architectures. - Pham Nam Khanh; Amit Kumar Singh 002; Akash Kumar 001 (ACM Great Lakes Symposium on VLSI, 2014)

Exploiting loop-array dependencies to accelerate the design space exploration with high level synthesis. - Pham Nam Khanh; Amit Kumar Singh 002; Akash Kumar 001; Khin Mi Mi Aung (DATE, 2015)

Automatic framework to generate reconfigurable accelerators for option pricing applications. - Pham Nam Khanh; Khin Mi Mi Aung; Akash Kumar 001 (ReConFig, 2016)

Machine Learning Approach to Generate Pareto Front for List-scheduling Algorithms. - Pham Nam Khanh; Akash Kumar 001; Khin Mi Mi Aung (SCOPES, 2016)

Leakage aware resource management approach with machine learning optimization framework for partially reconfigurable architectures. - Pham Nam Khanh; Akash Kumar 001; Amit Kumar Singh 002; Khin Mi Mi Aung (Microprocess. Microsystems, 2016)