A 1.4 V 10-bit 20 MSPS pipelined A/D converter. - Hee-Cheol Choi; Ho-Jin Park; Shin-Kyu Bae; Jae-Whui Kim; Philip Chung 003 (ISCAS, 2000)

A DLL based 10-320 MHz clock synchronizer. - Sung-Sik Hwang; Ki-Mo Joo; Ho-Jin Park; Jae-Whui Kim; Philip Chung 003 (ISCAS, 2000)

A 1 mW 10-bit 500KSPS SAR A/D converter. - Jaejin Park; Ho-Jin Park; Jae-Whui Kim; Sangnam Seo; Philip Chung 003 (ISCAS, 2000)

A 3.3 V 14-bit 10 MSPS calibration-free CMOS pipelined A/D converter. - Seung-Bin You; Ku-Whan Lee; Hee-Cheol Choi; Ho-Jin Park; Jae-Whui Kim; Philip Chung 003 (ISCAS, 2000)