Discrete-Time Modeling of Clock Jitter in Continuous-Time Delta Sigma Modulators. - Philip M. Chopp; Anas A. Hamoui (ISCAS, 2007)

Analysis of Clock-Jitter Effects in Continuous-Time Delta Sigma Modulators Using Discrete-Time Models. - Philip M. Chopp; Anas A. Hamoui (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Design Constraints for Image-Reject Frequency-Translating Delta Sigma Modulators. - Philip M. Chopp; Anas A. Hamoui (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A 1V 13mW frequency-translating ΔΣ ADC with 55dB SNDR for a 4MHz band at 225MHz. - Philip M. Chopp; Anas A. Hamoui (CICC, 2011)

A 1-V 13-mW Single-Path Frequency-Translating ΔΣ Modulator With 55-dB SNDR and 4-MHz Bandwidth at 225 MHz. - Philip M. Chopp; Anas A. Hamoui (IEEE J. Solid State Circuits, 2013)