FPGA-based rapid prototyping platform for MIMO-BICM design space exploration. - Christina Gimmler-Dumont; Philipp Schläfer; Norbert Wehn (ReConFig, 2012)

Design Space of Flexible Multigigabit LDPC Decoders. - Philipp Schläfer; Christian Weis; Norbert Wehn; Matthias Alles (VLSI Design, 2012)

ASIC implementation of a modified QR decomposition for tree search based MIMO detection. - Christina Gimmler-Dumont; Philipp Schläfer; Norbert Wehn (LASCAS, 2013)

Loopy - An open-source TCP/IP rapid prototyping and validation framework. - Christian de Schryver; Philipp Schläfer; Norbert Wehn; Thomas Fischer 003; Arnd Poetzsch-Heffter (ReConFig, 2013)

A new dimension of parallelism in ultra high throughput LDPC decoding. - Philipp Schläfer; Norbert Wehn; Matthias Alles; Timo Lehnigk-Emden (SiPS, 2013)

Syndrome based check node processing of high order NB-LDPC decoders. - Philipp Schläfer; Norbert Wehn; Matthias Alles; Timo Lehnigk-Emden; Emmanuel Boutillon (ICT, 2015)

A new architecture for high throughput, low latency NB-LDPC check node processing. - Philipp Schläfer; Vladimir Rybalkin; Norbert Wehn; Matthias Alles; Timo Lehnigk-Emden; Emmanuel Boutillon (PIMRC, 2015)

Error resilience and energy efficiency: An LDPC decoder design study. - Philipp Schläfer; Chu-Hsiang Huang; Clayton Schoeny; Christian Weis; Yao Li 007; Norbert Wehn; Lara Dolecek (DATE, 2016)

Saturated min-sum decoding: An "afterburner" for LDPC decoder hardware. - Stefan Scholl; Philipp Schläfer; Norbert Wehn (DATE, 2016)

A New Architecture for High Speed, Low Latency NB-LDPC Check Node Processing for GF(256). - Vladimir Rybalkin; Philipp Schläfer; Norbert Wehn (VTC Spring, 2016)

Implementation aspects of binary and non-binary low-density parity-check decoders = Implementierungsaspekte binärer und nicht-binärer Kanaldecodierer. - Philipp Schläfer (2017)