Robust wiring networks for DfY considering timing constraints. - Philipp V. Panitz; Markus Olbrich; Erich Barke; Jürgen Koehl (ACM Great Lakes Symposium on VLSI, 2007)

Considering possible opens in non-tree topology wire delay calculation. - Philipp V. Panitz; Markus Olbrich; Erich Barke; Markus Bühler; Jürgen Koehl (ACM Great Lakes Symposium on VLSI, 2008)

A theoretical probabilistic simulation framework for dynamic power estimation. - Lei Wang; Markus Olbrich; Erich Barke; Thomas Büchner; Markus Bühler; Philipp V. Panitz (ICCAD, 2011)

A gate sizing method for glitch power reduction. - Lei Wang; Markus Olbrich; Erich Barke; Thomas Büchner; Markus Bühler; Philipp V. Panitz (SoCC, 2011)