A quadrature direct digital downconverter. - Peter J. Vancorenland; Philippe Coppejans; Wouter De Cock; Michiel Steyaert (CICC, 2002)

Optimization of a fully integrated low power CMOS GPS receiver. - Peter J. Vancorenland; Philippe Coppejans; Wouter De Cock; Paul Leroux; Michiel Steyaert (ICCAD, 2002)

Dynamic biasing: a low power linearisation technique. - Philippe Coppejans; Michiel Steyaert (ESSCIRC, 2003)

Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification. - Lin-Kun Wu; David San Segundo Bello; Philippe Coppejans; Jan Craninckx; Andreas Süss; Maarten Rosmeulen; Piet Wambacq; Jonathan Borremans (Sensors, 2018)

A 0-to-35mA NMOS Capacitor-Less LDO with Dual-Loop Regulation Achieving 3ns Response Time and 1pF-to-10nF Loading Range. - Wen-Yang Hsu; Joan Aymerich; Xiaolin Yang; Chutham Sawigun; Philippe Coppejans; Carolina Mora Lopez (ESSCIRC, 2023)

A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for Full-Band Raw-Signal Recording. - Xiaolin Yang; Joan Aymerich; Philippe Coppejans; Wen-Yang Hsu; Chutham Sawigun; Jose Cisneros-Fernández; Andrea Lodi 003; Maribel Caceres Rivera; Bernardo Tacca; Matt McDonald; Hasan Mahmud-UI; Barundeb Dutta; et al. (VLSI Technology and Circuits, 2024)