Fast enumeration-based modulo scheduling heuristic for VLIW architectures. - Mounir Bahtat; Said Belkouch; Philippe Elleaume; Phillipe Le Gall (ICM, 2014)

Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect. - Abdessamad Klilou; Said Belkouch; Philippe Elleaume; Philippe Le Gall; François Bourzeix; Moha M'rabet Hassani (EURASIP J. Adv. Signal Process., 2014)

Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage. - Mounir Bahtat; Said Belkouch; Philippe Elleaume; Philippe Le Gall (EURASIP J. Adv. Signal Process., 2016)