Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. - Mario R. Casu; Philippe Flatresse (MTDT, 2002)

Electro-thermal short pulsed simulation for SOI technology. - Christophe Entringer; Philippe Flatresse; Philippe Galy; Florence Azaïs; Pascal Nouet (Microelectron. Reliab., 2006)

Bottom-up digital system-level reliability modeling. - N. Ruiz Amador; Vincent Huard; E. Pion; Florian Cacho; Damien Croain; V. Robert; Sylvain Engels; Philippe Flatresse; Lorena Anghel (CICC, 2011)

Comparison of 65nm LP bulk and LP PD-SOI with adaptive power gate body bias for an LDPC codec. - Julien Le Coz; Philippe Flatresse; Sylvain Engels; Alexandre Valentian; Marc Belleville; Christine Raynaud; Damien Croain; Pascal Urard (ISSCC, 2011)

Statistical Estimation of Dominant Physical Parameters for Leakage Variability in 32 Nanometer CMOS, Under Supply Voltage Variations. - Smriti Joshi; Anne Lombardot; Philippe Flatresse; Carmelo D'Agostino; Andre Juge; Edith Beigné; Stéphane Girard (J. Low Power Electron., 2012)

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs. - Edith Beigné; Alexandre Valentian; Bastien Giraud; Olivier Thomas; Thomas Benoist; Yvain Thonnart; Serge Bernard; Guillaume Moritz; Olivier Billoint; Y. Maneglia; Philippe Flatresse; Jean-Philippe Noel; et al. (DATE, 2013)

UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency. - Philippe Magarshack; Philippe Flatresse; Giorgio Cesana (DATE, 2013)

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI. - Kaya Can Akyel; Lorenzo Ciampolini; Olivier Thomas; Bertrand Pelloux-Prayer; Shishir Kumar; Philippe Flatresse; Christophe Lecocq; Gérard Ghibaudo (ISCAS, 2013)

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology. - Philippe Flatresse; Bastien Giraud; Jean-Philippe Noel; Bertrand Pelloux-Prayer; Fabien Giner; Deepak-Kumar Arora; Franck Arnaud; Nicolas Planes; Julien Le Coz; Olivier Thomas; Sylvain Engels; Giorgio Cesana; et al. (ISSCC, 2013)

Fine grain multi-VT co-integration methodology in UTBB FD-SOI technology. - Bertrand Pelloux-Prayer; Alexandre Valentian; Bastien Giraud; Yvain Thonnart; Jean-Philippe Noel; Philippe Flatresse; Edith Beigné (VLSI-SoC, 2013)

Process and design solutions for exploiting FD-SOI technology towards energy efficient SOCs. - Philippe Flatresse (ISLPED, 2014)

27.7 A scalable 1.5-to-6Gb/s 6.2-to-38.1mW LDPC decoder for 60GHz wireless networks in 28nm UTBB FDSOI. - Matthew Weiner; Milovan Blagojevic; Sergey Skotnikov; Andreas Burg 001; Philippe Flatresse; Borivoje Nikolic (ISSCC, 2014)

27.1 A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding FMAX tracking. - Robin Wilson; Edith Beigné; Philippe Flatresse; Alexandre Valentian; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; Anuj Grover; et al. (ISSCC, 2014)

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization. - David Jacquet; Frederic Hasbani; Philippe Flatresse; Robin Wilson; Franck Arnaud; Giorgio Cesana; Thierry Di Gilio; Christophe Lecocq; Tanmoy Roy; Amit Chhabra; Chiranjeev Grover; Olivier Minez; et al. (IEEE J. Solid State Circuits, 2014)

PULP: A parallel ultra low power platform for next generation IoT applications. - Davide Rossi; Francesco Conti 001; Andrea Marongiu; Antonio Pullini; Igor Loi; Michael Gautschi; Giuseppe Tagliavini; Alessandro Capotondi; Philippe Flatresse; Luca Benini (Hot Chips Symposium, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking. - Edith Beigné; Alexandre Valentian; Ivan Miro Panades; Robin Wilson; Philippe Flatresse; Fady Abouzeid; Thomas Benoist; Christian Bernard; Sebastien Bernard; Olivier Billoint; Sylvain Clerc; Bastien Giraud; et al. (IEEE J. Solid State Circuits, 2015)

193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Fady Abouzeid; et al. (COOL Chips, 2016)

A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI. - Milovan Blagojevic; Martin Cochet; Ben Keller; Philippe Flatresse; Andrei Vladimirescu; Borivoje Nikolic (VLSI Circuits, 2016)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

Temperature and process-aware performance monitoring and compensation for an ULP multi-core cluster in 28nm UTBB FD-SOI technology. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (PATMOS, 2017)

A Self-Aware Architecture for PVT Compensation and Power Nap in Near Threshold Processors. - Davide Rossi; Igor Loi; Antonio Pullini; Thomas Christoph Müller; Andreas Burg 001; Francesco Conti 001; Luca Benini; Philippe Flatresse (IEEE Des. Test, 2017)

PolarBear: A 28-nm FD-SOI ASIC for Decoding of Polar Codes. - Pascal Giard; Alexios Balatsoukas-Stimming; Thomas Christoph Müller; Andrea Bonetti; Claude Thibeault; Warren J. Gross; Philippe Flatresse; Andreas Burg 001 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2017)

Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. - Davide Rossi; Antonio Pullini; Igor Loi; Michael Gautschi; Frank Kagan Gürkaynak; Adam Teman; Jeremy Constantin; Andreas Burg 001; Ivan Miro Panades; Edith Beigné; Fabien Clermidy; Philippe Flatresse; et al. (IEEE Micro, 2017)

Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. - Andrea Bonetti; Adam Teman; Philippe Flatresse; Andreas Burg 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 32 kb 0.35-1.2 V, 50 MHz-2.5 GHz Bit-Interleaved SRAM With 8 T SRAM Cell and Data Dependent Write Assist in 28-nm UTBB-FDSOI CMOS. - Anuj Grover; G. S. Visweswaran; Chittoor R. Parthasarathy; Mohammad Daud; David Turgis; Bastien Giraud; Jean-Philippe Noel; Ivan Miro Panades; Guillaume Moritz; Edith Beigné; Philippe Flatresse; Promod Kumar; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Resilient automotive products through process, temperature and aging compensation schemes. - Souhir Mhira; Vincent Huard; D. Arora; Philippe Flatresse; Alain Bravaix (IRPS, 2018)

Live Demonstration: Body-Bias Based Performance Monitoring and Compensation for a Near-Threshold Multi-Core Cluster in 28nm FD-SOI Technology. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (ISCAS, 2018)

A 2.5μW 0.0067mm2 automatic back-biasing compensation unit achieving 50% leakage reduction in FDSOI 28nm over 0.35-to-1V VDD range. - Anthony Quelen; Gaël Pillonnet; Philippe Flatresse; Edith Beigné (ISSCC, 2018)

Performance-Aware Predictive-Model-Based On-Chip Body-Bias Regulation Strategy for an ULP Multi-Core Cluster in 28nm UTBB FD-SOI. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (CoRR, 2020)

Performance-aware predictive-model-based on-chip body-bias regulation strategy for an ULP multi-core cluster in 28 nm UTBB FD-SOI. - Alfio Di Mauro; Davide Rossi; Antonio Pullini; Philippe Flatresse; Luca Benini (Integr., 2020)

A 0.021mm2 PVT-Aware Digital-Flow-Compatible Adaptive Back-Biasing Regulator with Scalable Drivers Achieving 450% Frequency Boosting and 30% Power Reduction in 22nm FDSOI Technology. - Yasser Moursy; Thiago Raupp da Rosa; Lionel Jure; Anthony Quelen; Sébastien Genevey; Lionel Pierrefeu; Emmanuel G. Collins Jr.; Joerg Winkler; Jonathan Park; Gaël Pillonnet; Vincent Huard; Andrea Bonzo; et al. (ISSCC, 2021)