Simulation and experimental comparison of GGNMOS and LVTSCR protection cells under ElectroStatic Discharges. - A. Guilhaume; Philippe Galy; J. P. Chante; B. Foucher; F. Blanc (Microelectron. Reliab., 2001)

Experimental and 3D simulation correlation of a gg-nMOS transistor under high current pulse. - Philippe Galy; V. Berland; B. Foucher; A. Guilhaume; J. P. Chante; S. Bardy; F. Blanc (Microelectron. Reliab., 2002)

Experimental measurements and 3D simulation of the parasitic lateral bipolar transistor triggering within a single finger gg-nMOS under ESD. - Philippe Galy; V. Berland; A. Guilhaume; F. Blanc; J. P. Chante (Microelectron. Reliab., 2004)

Electro-thermal short pulsed simulation for SOI technology. - Christophe Entringer; Philippe Flatresse; Philippe Galy; Florence Azaïs; Pascal Nouet (Microelectron. Reliab., 2006)

Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress. - Philippe Galy; Sylvain Dudit; Michel Vallet; Corinne Richier; Christophe Entringer; Frank Jezequel; E. Petit; J. Beltritti (Microelectron. Reliab., 2009)

Evaluation of the ESD performance of local protections based on SCR or bi-SCR with dynamic or static trigger circuit in 32 nm. - J. Bourgeat; Christophe Entringer; Philippe Galy; Marise Bafleur; D. Marin-Cudraz (Microelectron. Reliab., 2010)

Inventory of silicon signatures induced by CDM event on deep sub-micronic CMOS-BICMOS technologies. - Philippe Galy; Sylvain Dudit; Michel Vallet; Ph. Larre; M. Bilinski; E. Petit; J. Beltritti; A. Dray; Jean Jimenez; Frank Jezequel; R. Chevallier; C. Boutonnat; et al. (Microelectron. Reliab., 2010)

A full characterization of single pitch IO ESD protection based on silicon controlled rectifier and dynamic trigger circuit in CMOS 32 nm node. - J. Bourgeat; Philippe Galy; A. Dray; Jean Jimenez; D. Marin-Cudraz; Blaise Jacquier (Microelectron. Reliab., 2011)

Reliability impact due to high current, lattice and hot carriers temperatures on β(2×2) matrix ESD power devices for advanced CMOS technologies. - Philippe Galy; J. Bourgeat; Jean Jimenez; Blaise Jacquier; D. Marin-Cudraz; Sylvain Dudit (Microelectron. Reliab., 2011)

BIMOS transistor and its applications in ESD protection in advanced CMOS technology. - Philippe Galy; Jean Jimenez; Johan Bourgeat; A. Dray; Ghislain Troussier; Boris Heitz; Nicolas Guitard; David Marin-Cudraz; H. Beckrich-Ros (ICICDT, 2012)

High swing low capacitance ESD RF protections in advanced CMOS technologies. - Jean Jimenez; Philippe Galy; Johan Bourgeat; Boris Heitz (ICICDT, 2012)

Symmetrical ESD trigger and pull-up using BIMOS transistor in advanced CMOS technology. - Philippe Galy; Johan Bourgeat; Jean Jimenez; Nicolas Guitard; Alexandre Dray; Ghislain Troussier; Blaise Jacquier; David Marin-Cudraz (Microelectron. Reliab., 2012)

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control. - Vivek Asthana; Malathi Kar; Jean Jimenez; Jean-Philippe Noel; Sébastien Haendler; Philippe Galy (ESSCIRC, 2013)

6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology. - Vivek Asthana; Malathi Kar; Jean Jimenez; Sébastien Haendler; Philippe Galy (ICICDT, 2013)

ESD protection using BIMOS transistor in 100 GHz RF application for advanced CMOS technology. - Philippe Galy; T. Lim; Jean Jimenez; Boris Heitz; Ph. Benech; J. M. Fournier; D. Marin-Cudraz (ICICDT, 2013)

Symmetrical ESD protection for advanced CMOS technology dedicated to 100 GHz RF application. - Philippe Galy; T. Lim; J. Bourgeat; Jean Jimenez; Boris Heitz; D. Marin-Cudraz; Ph. Benech; J. M. Fournier (Microelectron. Reliab., 2013)

New modular bi-directional power-switch and self ESD protected in 28nm UTBB FDSOI advanced CMOS technology. - Philippe Galy; J. Bourgeat; D. Marin-Cudraz (ICICDT, 2014)

Computation of Self-Induced Magnetic Field Effects Including the Lorentz Force for Fast-Transient Phenomena in Integrated-Circuit Devices. - Wim Schoenmaker; Quan Chen; Philippe Galy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Preliminary 3D TCAD electro-thermal simulations of BIMOS transistor in thin silicon film for ESD protection in FDSOI UTBB CMOS technology. - S. Athanasiou; Sorin Cristoloveanu; Philippe Galy (ICICDT, 2015)

Integrated front-end/back-end simulation of electromagnetic fields, Lorentz force effects and fast current surges in microelectronic protection devices. - Wim Schoenmaker; Philippe Galy (ICICDT, 2015)

Coupled electro-magnetic field & Lorentz force effects in silicon and metal for ESD investigation in transient and harmonic regimes. - Philippe Galy; Wim Schoenmaker (Microelectron. Reliab., 2015)

Preliminary results on TFET - Gated diode in thin silicon film for IO design & ESD protection in 28nm UTBB FD-SOI CMOS technology. - Philippe Galy; S. Athanasiou (ICICDT, 2016)

On the need for a new ESD verification methodology to improve the reliability of ICs in advanced 28nm UTBB FD-SOI technology. - Benjamin Viale; Mathieu Fer; Lionel Courau; Philippe Galy; Bruno Allard (Microelectron. Reliab., 2016)

Toward Gated-Diode-BIMOS for thin silicon ESD protection in advanced FD-SOI CMOS technologies. - Louise De Conti; Thomas Bedecarrats; Maud Vinet; Sorin Cristoloveanu; Philippe Galy (ICICDT, 2017)

Exploration of robustness limits and ESD EMI impact in a protection device for advanced CMOS technology. - Philippe Galy; Wim Schoenmaker (Microelectron. Reliab., 2017)

Optimized in situ heating control on a new MOS device structure in 28nm UTBB FD-SOI CMOS technology. - Philippe Galy; R. Lethiecq; Maryline Bawedin (ICICDT, 2018)

Simulation, characterization and implementation of a new SCR-based device with a turn-off capability for EOS-immune ESD power supply clamps in advanced CMOS technology nodes. - Jorge Loayza; Nicolas Guitard; Bruno Allard; Luong-Viêt Phung; Blaise Jacquier; Philippe Galy (Microelectron. Reliab., 2018)

Temperature and Gate Leakage Influence on the Z2-FET Memory Operation. - Carlos Marquez; Santiago Navarro; Carlos Navarro; Norberto Salazar; Philippe Galy; Sorin Cristoloveanu; Francisco Gámiz (ESSDERC, 2019)

1T1C Ultra low power relative Thermal-Voltage sensor in 28nm UTBB FD-SOI CMOS technology for standard, spatial and quantum applications. - Philippe Galy; R. Lethiecq; Maryline Bawedin (ICICDT, 2019)

Compact MOS Structure & Design for Ion-Ioff Thermal control in 28nm UTBB FD-SOI CMOS technology. - R. Lethiecq; Maryline Bawedin; Philippe Galy (ICICDT, 2019)

10Gbps Length adaptive on-chip RF serial link for Network on Chips and Multiprocessor chips applications. - Mohammed Tmimi; Stefano D'Amico; Jean-Marc Duchamp; Philippe Ferrari; Philippe Galy (ICICDT, 2019)

Thin-Film FD-SOI BIMOS Topologies for ESD Protection. - Louise De Conti; Sorin Cristoloveanu; Maud Vinet; Philippe Galy (IRPS, 2019)

On the Low-Frequency Noise Characterization of Z2-FET Devices. - Carlos Marquez; Carlos Navarro; Santiago Navarro; José Luis Padilla; Luca Donetti; Carlos Sampedro 002; Philippe Galy; Yong-Tae Kim; Francisco Gámiz (IEEE Access, 2019)

7-mm low-latency inter-chiplet serial link with silicon interposer. - Mohammed Tmimi; Stefano D'Amico; Jean-Marc Duchamp; Philippe Ferrari; Philippe Galy (MWSCAS, 2020)

Fast Measurement of BTI on 28nm Fully Depleted Silicon-On-Insulator MOSFETs at Cryogenic Temperature down to 4K. - Lauriane Contamin; Mikaël Cassé; Xavier Garros; Fred Gaillard; Maud Vinet; Philippe Galy; André Juge; Emmanuel Vincent 004; Silvano De Franceschi; Tristan Meunier (IRPS, 2022)

Noise modeling using look-up tables and DC measurements for cryogenic applications. - Giovani Britton; Salvador Mir; Estelle Lauga-Larroze; Benjamin Dormieu; Quentin Berlingard; Mikaël Cassé; Philippe Galy (VLSI-SoC, 2023)

A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses. - Joao Henrique Quintino Palhares; Yann Beilliard; Jury Sandrini; Franck Arnaud; Kevin Garello; Guillaume Prenat; Lorena Anghel; Fabien Alibart; Dominique Drouin; Philippe Galy (CoRR, 2023)

LUT-Based Design of a Cryogenic Cascode LNA with Simultaneous Noise and Power Matching. - Giovani Britton; Salvador Mir; Estelle Lauga-Larroze; Benjamin Dormieu; Jose Lugo; Joao Azevedo; Sebastien Sadlo; Quentin Berlingard; Mikaël Cassé; Philippe Galy (NewCAS, 2024)

28 nm FD-SOI 4 K RF LNA Design Using DC Transistor Characterization Measurements. - Giovani Britton; Salvador Mir; Estelle Lauga-Larroze; Benjamin Dormieu; Jose Lugo; Joao Azevedo; Sebastien Sadlo; Quentin Berlingard; Mickael Casse; Philippe Galy (LATS, 2025)