An ACL2 Model of VHDL for Symbolic Simulation and Formal Verification. - Vanderlei Moraes Rodrigues; Dominique Borrione; Philippe Georgelin (SBCCI, 2000)

Using the ACL2 Theorem Prover to Reason about VHDL Components. - Vanderlei Moraes Rodrigues; Dominique Borrione; Philippe Georgelin (RITA, 2000)

Vérification formelle de systèmes digitaux synchrones, basée sur la simulation symbolique. (Formal verification of synchronous digital designs, based on symbolic simulation). - Philippe Georgelin (2001)

Towards a C++-based design methodology facilitating sequential equivalence checking. - Philippe Georgelin; Venkat Krishnaswamy (DAC, 2006)

Peak power estimation using activity measured on emulator. - Christian Berthet; Philippe Georgelin; Janvier Ntyame; Mathieu Raffin (ICECS, 2012)