FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA. - François Duhem; Fabrice Muller; Philippe Lorenzini (ARC, 2011)

Methodology for designing partially reconfigurable systems using transaction-level modeling. - François Duhem; Fabrice Muller; Philippe Lorenzini (DASIP, 2011)

Reconfiguration time overhead on field programmable gate arrays: reduction and cost model. - François Duhem; Fabrice Muller; Philippe Lorenzini (IET Comput. Digit. Tech., 2012)

Design space exploration for partially reconfigurable architectures in real-time systems. - François Duhem; Fabrice Muller; Willy Aubry; Bertrand Le Gal; Daniel Négru; Philippe Lorenzini (J. Syst. Archit., 2013)

Dynamically reconfigurable entropy coder for multi-standard video adaptation using FaRM. - François Duhem; Nicolas Marques; Fabrice Muller; Hassan Rabah; Serge Weber; Philippe Lorenzini (Microprocess. Microsystems, 2013)

VCO design in SOI technologies. - Alexandre Fonseca; Gilles Jacquemod; Yves Leduc; Emeric de Foucauld; Philippe Lorenzini (NEWCAS, 2014)

Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop. - Alexandre Fonseca; Emeric de Foucauld; Philippe Lorenzini; Gilles Jacquemod (J. Low Power Electron., 2014)

Study and Reduction of Variability in 28 nm Fully Depleted Silicon on Insulator Technology. - Zhaopeng Wei; Gilles Jacquemod; Philippe Lorenzini; Frédéric Hameau; Emeric de Foucauld; Yves Leduc (J. Low Power Electron., 2016)

Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology. - Paul Devoge; Hassen Aziza; Philippe Lorenzini; Franck Julien; Abderrezak Marzaki; Alexandre Malherbe; Marc Mantelli; Thomas Sardin; Sébastien Haendler; Arnaud Régnier; Stephan Niel (DTIS, 2021)

A Schmitt trigger to benchmark the performance of a new zero-cost transistor. - Paul Devoge; Hassen Aziza; Philippe Lorenzini; Pascal Masson; Alexandre Malherbe; Franck Julien; Abderrezak Marzaki; Arnaud Régnier; Stephan Niel (ICECS 2022, 2022)

Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor. - Paul Devoge; Hassen Aziza; Philippe Lorenzini; Alexandre Malherbe; Franck Julien; Abderrezak Marzaki; Arnaud Régnier; Stephan Niel (ISCAS, 2022)

40nm SONOS Embedded Select in Trench Memory. - Radouane Habhab; Vincenzo Della Marca; Pascal Masson; Nadia Miridi; Clement Pribat; Simon Jeannot; Thibault Kempf; Marc Mantelli; Philippe Lorenzini; Jean-Marc Voisin; Arnaud Régnier; Stephan Niel; et al. (ESSDERC, 2023)