A 1.0ns 64-bits GaAs Adder using Quad tree algorithm. - Philippe Royannez; Amara Amara (Great Lakes Symposium on VLSI, 1996)

A design platform for 90-nm leakage reduction techniques. - Philippe Royannez; Hugh Mair; Franck Dahan; Mike Wagner; Mark Streeter; Laurent Bouetel; Joel Blasquez; H. Clasen; G. Semino; Julie Dong; D. Scott; B. Pitts; et al. (DAC, 2005)

Solutions for logic and processor core design at the 45nm technology node & and below. - Philippe Royannez; Hugh Mair; Michael Clinton; Uming Ko (ICECS, 2007)

TD: Proximity Data and Power Transmission. - Chris Van Hoof; Philippe Royannez (ISSCC, 2007)

A 45nm 3.5G Baseband-and-Multimedia Application Processor using Adaptive Body-Bias and Ultra-Low-Power Techniques. - Gordon Gammie; Alice Wang; Minh Chau; Sumanth Gururajarao; Robert Pitts; Fabien Jumel; Stacey Engel; Philippe Royannez; Rolf Lagerquist; Hugh Mair; Jeff Vaccani; Greg Baldwin; et al. (ISSCC, 2008)

SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors. - Gordon Gammie; Alice Wang; Hugh Mair; Rolf Lagerquist; Minh Chau; Philippe Royannez; Sumanth Gururajarao; Uming Ko (Proc. IEEE, 2010)

Practical and efficient SOC verification flow by reusing IP testcase and testbench. - Zhaohui Hu; Arnaud Pierres; Shiqing Hu; Chen Fang; Philippe Royannez; Eng Pek See; Yean Ling Hoon (ISOCC, 2012)

BIST Methodology, Architecture and Circuits for Pre-Bond TSV Testing in 3D Stacking IC Systems. - Chao Wang 016; Jun Zhou 017; Roshan Weerasekera; Bin Zhao; Xin Liu 015; Philippe Royannez; Minkyu Je (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)