Phillip H. Jones

According to our database, Phillip H. Jones authored at least 68 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Model Predictive Runtime Verification for Cyber-Physical Systems with Real-Time Deadlines.

Pei Zhang, Alexis A. Aurandt, Rohit Dureja, Phillip H. Jones, Kristin Yvonne Rozier

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2023

Maximum Satisfiability of Mission-Time Linear Temporal Logic.

Gokul Hariharan, Phillip H. Jones, Kristin Yvonne Rozier, Tichakorn Wongpiromsarn

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2023

Impossible Made Possible: Encoding Intractable Specifications via Implied Domain Constraints.

Chris Johannsen, Brian Kempa, Phillip H. Jones, Kristin Y. Rozier, Tichakorn Wongpiromsarn

Proceedings of the Formal Methods for Industrial Critical Systems, 2023

Case Studies in Applying Design Thinking to Course Design in Computer Engineering.

Diane T. Rover, Henry Duwe, Phillip H. Jones, Nicholas D. Fila, Mani Mina

Proceedings of the IEEE Frontiers in Education Conference, 2023

R2U2 Version 3.0: Re-Imagining a Toolchain for Specification, Resource Estimation, and Optimized Observer Generation for Runtime Verification in Hardware and Software.

Chris Johannsen, Phillip H. Jones, Brian Kempa, Kristin Yvonne Rozier, Pei Zhang

Proceedings of the Computer Aided Verification - 35th International Conference, 2023

2022

Integrating runtime verification into an automated UAS traffic management system.

Abigail Hammer, Matthew Cauwels, Benjamin Hertz, Phillip H. Jones, Kristin Y. Rozier

Innov. Syst. Softw. Eng., 2022

Runtime Verification Triggers Real-Time, Autonomous Fault Recovery on the CySat-I.

Alexis A. Aurandt, Phillip H. Jones, Kristin Yvonne Rozier

Proceedings of the NASA Formal Methods - 14th International Symposium, 2022

Defining and Supporting a Debugging Mindset in Computer Engineering Courses.

Henry Duwe, Diane T. Rover, Phillip H. Jones, Nicholas D. Fila, Mani Mina

Proceedings of the IEEE Frontiers in Education Conference, 2022

MLTL Multi-type (MLTLM): A Logic for Reasoning About Signals of Different Types.

Gokul Hariharan, Brian Kempa, Tichakorn Wongpiromsarn, Phillip H. Jones, Kristin Y. Rozier

Proceedings of the Software Verification and Formal Methods for ML-Enabled Autonomous Systems, 2022

2021

Benchmarking vision kernels and neural network inference accelerators on embedded platforms.

Murad Qasaimeh, Kristof Denolf, Alireza Khodamoradi, Michaela Blott, Jack Lo, Lisa Halder, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones

J. Syst. Archit., 2021

Learning and Professional Development Through Integrated Reflective Activities in Electrical and Computer Engineering Courses.

Diane T. Rover, Henry J. Duwe III, Mani Mina, Nicholas D. Fila, Phillip H. Jones, Lindsey S. Sleeth

Proceedings of the IEEE Frontiers in Education Conference, 2021

An Efficient Hardware Architecture for Sparse Convolution using Linear Feedback Shift Registers.

Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

Embedding Online Runtime Verification for Fault Disambiguation on Robonaut2.

Brian Kempa, Pei Zhang, Phillip H. Jones, Joseph Zambreno, Kristin Yvonne Rozier

Proceedings of the Formal Modeling and Analysis of Timed Systems, 2020

Introducing Autonomy in an Embedded Systems Course Project.

Diane T. Rover, Nicholas D. Fila, Phillip H. Jones, Mani Mina

Proceedings of the IEEE Frontiers in Education Conference, 2020

ParaHist: FPGA Implementation of Parallel Event-Based Histogram for Optical Flow Calculation.

Mohammad Pivezhandi, Phillip H. Jones, Joseph Zambreno

Proceedings of the 31st IEEE International Conference on Application-specific Systems, 2020

2019

Comparing Energy Efficiency of CPU, GPU and FPGA Implementations for Vision Kernels.

Murad Qasaimeh, Kristof Denolf, Jack Lo, Kees A. Vissers, Joseph Zambreno, Phillip H. Jones

Proceedings of the 15th IEEE International Conference on Embedded Software and Systems, 2019

Analyzing the Energy-Efficiency of Vision Kernels on Embedded CPU, GPU and FPGA Platforms.

Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones, Kristof Denolf, Jack Lo, Kees A. Vissers

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018

ARMOR: A Recompilation and Instrumentation-Free Monitoring Architecture for Detecting Memory Exploits.

Alex Grieve, Michael Davies, Phillip H. Jones, Joseph Zambreno

IEEE Trans. Computers, 2018

HW/SW Configurable LQG Controller using a Sequential Discrete Kalman Filter.

Matthew Cauwels, Joseph Zambreno, Phillip H. Jones

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

An FPGA-based Hardware Accelerator for Iris Segmentation.

Joe Avey, Phillip H. Jones, Joseph Zambreno

Proceedings of the 2018 International Conference on ReConFigurable Computing and FPGAs, 2018

A Runtime Configurable Hardware Architecture for Computing Histogram-Based Feature Descriptors.

Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

The design and integration of a software configurable and parallelized coprocessor architecture for LQR control.

Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones

J. Parallel Distributed Comput., 2017

A Modified Sliding Window Architecture for Efficient BRAM Resource Utilization.

Murad Qasaimeh, Joseph Zambreno, Phillip H. Jones

Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

An embedded scalable linear model predictive hardware-based controller using ADMM.

Pei Zhang, Joseph Zambreno, Phillip H. Jones

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017

2016

A Reconfigurable Architecture for the Detection of Strongly Connected Components.

Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno

ACM Trans. Reconfigurable Technol. Syst., 2016

RAMPS: A Reconfigurable Architecture for Minimal Perfect Sequencing.

Chad Nelson, Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno

IEEE Trans. Parallel Distributed Syst., 2016

Parameterizable FPGA-Based Kalman Filter Coprocessor Using Piecewise Affine Modeling.

Aaron Mills, Phillip H. Jones, Joseph Zambreno

Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Evidence-based planning to broaden the participation of women in electrical and computer engineering.

Diane T. Rover, Joseph Zambreno, Mani Mina, Phillip H. Jones, Lora Leigh Chrystal

Proceedings of the 2016 IEEE Frontiers in Education Conference, 2016

2015

A Fault-Aware Toolchain Approach for FPGA Fault Tolerance.

Adwait Gupte, Sudhanshu Vyas, Phillip H. Jones

ACM Trans. Design Autom. Electr. Syst., 2015

A Configurable Architecture for Sparse LU Decomposition on Matrices with Arbitrary Patterns.

Xinying Wang, Phillip H. Jones, Joseph Zambreno

SIGARCH Comput. Archit. News, 2015

An FPGA Architecture for the Recovery of WPA/WPA2 Keys.

Tyler Johnson, Daniel Roggow, Phillip H. Jones, Joseph Zambreno

J. Circuits Syst. Comput., 2015

A Scalable Unsegmented Multiport Memory for FPGA-Based Systems.

Kevin R. Townsend, Osama G. Attia, Phillip H. Jones, Joseph Zambreno

Int. J. Reconfigurable Comput., 2015

A software configurable and parallelized coprocessor architecture for LQR control.

Pei Zhang, Aaron Mills, Joseph Zambreno, Phillip H. Jones

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

Accelerating all-pairs shortest path using a message-passing reconfigurable architecture.

Osama G. Attia, Alex Grieve, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno

Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

A project-based embedded systems design course using a reconfigurable SoC platform.

Daniel Roggow, Paul Uhing, Phillip H. Jones, Joseph Zambreno

Proceedings of the 2015 IEEE International Conference on Microelectronics Systems Education, 2015

A software configurable coprocessor-based state-space controller.

Aaron Mills, Pei Zhang, Sudhanshu Vyas, Joseph Zambreno, Phillip H. Jones

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

k-NN text classification using an FPGA-based sparse matrix vector multiplication accelerator.

Kevin R. Townsend, Song Sun, Tyler Johnson, Osama G. Attia, Phillip H. Jones, Joseph Zambreno

Proceedings of the IEEE International Conference on Electro/Information Technology, 2015

2014

Hardware-software architecture for priority queue management in real-time and embedded systems.

N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones

Int. J. Embed. Syst., 2014

An FPGA-Based Plant-on-Chip Platform for Cyber-Physical System Analysis.

Sudhanshu Vyas, Chetan Kumar Ng, Joseph Zambreno, Christopher D. Gill, Ron Cytron, Phillip H. Jones

IEEE Embed. Syst. Lett., 2014

A high performance systolic architecture for k-NN classification.

Kevin Townsend, Phillip H. Jones, Joseph Zambreno

Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

A Reconfigurable Architecture for QR Decomposition Using a Hybrid Approach.

Xinying Wang, Phillip H. Jones, Joseph Zambreno

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

CyGraph: A Reconfigurable Architecture for Parallel Breadth-First Search.

Osama G. Attia, Tyler Johnson, Kevin Townsend, Phillip H. Jones, Joseph Zambreno

Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

Cache design for mixed criticality real-time systems.

N. G. Chetan Kumar, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Hardware architectural support for control systems and sensor processing.

Sudhanshu Vyas, Adwait Gupte, Christopher D. Gill, Ron K. Cytron, Joseph Zambreno, Phillip H. Jones

ACM Trans. Embed. Comput. Syst., 2013

Design and implementation of an H∞ controller for a quadrotor helicopter.

Matt Rich, Nicola Elia, Phillip H. Jones

Proceedings of the 21st Mediterranean Conference on Control and Automation, 2013

Scheduling Challenges in Mixed Critical Real-Time Heterogeneous Computing Platforms.

Chetan Kumar Ng, Sudhanshu Vyas, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones

Proceedings of the International Conference on Computational Science, 2013

2012

An I/O Bandwidth-Sensitive Sparse Matrix-Vector Multiplication Engine on FPGAs.

Song Sun, Madhu Monga, Phillip H. Jones, Joseph Zambreno

IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Improving System Predictability and Performance via Hardware Accelerated Data Structures.

Chetan Kumar Ng, Sudhanshu Vyas, Jonathan A. Shidal, Ron K. Cytron, Christopher D. Gill, Joseph Zambreno, Phillip H. Jones

Proceedings of the International Conference on Computational Science, 2012

Shepard: A fast exact match short read aligner.

Chad Nelson, Kevin Townsend, Bhavani Satyanarayana Rao, Phillip H. Jones, Joseph Zambreno

Proceedings of the Tenth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2012

Design and evaluation of a delay-based FPGA Physically Unclonable Function.

Aaron Mills, Sudhanshu Vyas, Michael Patterson, Christopher Sabotta, Phillip H. Jones, Joseph Zambreno

Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011

Characterizing Non-ideal Impacts of Reconfigurable Hardware Workloads on Ring Oscillator-Based Thermometers.

Moinuddin Sayed, Phillip H. Jones

Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

Teaching graphics processing and architecture using a hardware prototyping approach.

Michael Steffen, Phillip H. Jones, Joseph Zambreno

Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

Circumventing a ring oscillator approach to FPGA-based hardware Trojan detection.

Justin Rilling, David Graziano, Jamin Hitchcock, Tim Meyer, Xinying Wang, Phillip H. Jones, Joseph Zambreno

Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2010

Team [Ii][Ss][Uu][0-2]{4} design overview: MEMOCODE 2010 design contest.

Sudhanshu Vyas, Pooja Mhapsekar, Aditya Ashok, Moinuddin Sayed, Avinash Srinivasa, Gunjan Pandey, Adam Jackson, Matthew Nelson, Anand Saggi, Harini Sundararaman, Phillip H. Jones

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

CANSCID-CUDA.

Michael Steffen, Veerendra Allada, Phillip H. Jones, Joseph Zambreno

Proceedings of the 8th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2010), 2010

An evaluation of a slice fault aware tool chain.

Adwait Gupte, Phillip H. Jones

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Towards Hardware Support for Common Sensor Processing Tasks.

Adwait Gupte, Phillip H. Jones

Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Hotspot Mitigation Using Dynamic Partial Reconfiguration for Improved Performance.

Adwait Gupte, Phillip H. Jones

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2007

Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads.

Phillip H. Jones, Young H. Cho, John W. Lockwood

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Adaptive Thermoregulation for Applications on Reconfigurable Devices.

Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood

Proceedings of the FPL 2007, 2007

Changing Output Quality for Thermal Management.

Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006

An adaptive frequency control method using thermal feedback for reconfigurable hardware applications.

Phillip H. Jones, Young H. Cho, John W. Lockwood

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

A Thermal Management and Profiling Method for Reconfigurable Hardware Applications.

Phillip H. Jones, John W. Lockwood, Young H. Cho

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures.

Shobana Padmanabhan, Phillip H. Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger D. Chamberlain, Ron Cytron, Jason E. Fritts, John W. Lockwood

Int. J. Parallel Program., 2005

Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory.

Roger D. Chamberlain, John W. Lockwood, Saurabh Gayen, Richard Hough, Phillip H. Jones

Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

2004

The Effects of an ARMOR-Based SIFT Environment on the Performance and Dependability of User Applications.

Keith Whisnant, Ravishankar K. Iyer, Zbigniew Kalbarczyk, Phillip H. Jones III, David A. Rennels, Raphael R. Some

IEEE Trans. Software Eng., 2004

Liquid Architecture.

Phillip H. Jones, Shobana Padmanabhan, Daniel Rymarz, John Maschmeyer, David V. Schuehler, John W. Lockwood, Ron Cytron

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

2002

NFTAPE: Networked Fault Tolerance and Performance Evaluator.

David T. Stott, Phillip H. Jones III, M. Hamman, Zbigniew Kalbarczyk, Ravishankar K. Iyer

Proceedings of the 2002 International Conference on Dependable Systems and Networks (DSN 2002), 2002