Fast CMOS ECL receivers with 100-mV worst-case sensitivity. - Barbara A. Chappell; Terry I. Chappell; Stanley E. Schuster; Hermann M. Segmuller; James W. Allan; Robert L. Franch; Phillip J. Restle (IEEE J. Solid State Circuits, 1988)

A 3.5 ns/77 K and 6.2 ns/300 K 64 K CMOS RAM with ECL interfaces. - Terry I. Chappell; Stanley E. Schuster; Barbara A. Chappell; James W. Allan; Jack Y.-C. Sun; Stephen P. Klepner; Robert L. Franch; Paul F. Greier; Phillip J. Restle (IEEE J. Solid State Circuits, 1989)

A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders. - Charles F. Webb; Carl J. Anderson; Leon J. Sigal; Kenneth L. Shepard; John S. Liptay; James D. Warnock; Brian W. Curran; Barry Krumm; Mark D. Mayo; Peter J. Camporese; Eric M. Schwarz; Mark S. Farrell; et al. (IEEE J. Solid State Circuits, 1997)

Interconnect in high speed designs: problems, methodologies and tools. - Phillip J. Restle; Joel R. Phillips; Ibrahim M. Elfadel (ICCAD, 1998)

Measurement and modeling of on-chip transmission line effects in a 400 MHz microprocessor. - Phillip J. Restle; Keith A. Jenkins; Alina Deutsch; Peter W. Cook (IEEE J. Solid State Circuits, 1998)

Dealing with Inductance in High-Speed Chip Design. - Phillip J. Restle; Albert E. Ruehli; Steven G. Walker (DAC, 1999)

Technical Visualizations in VLSI Design. - Phillip J. Restle (DAC, 2001)

Multi-GHz interconnect effects in microprocessors. - Phillip J. Restle; Albert E. Ruehli; Steven G. Walker (ISPD, 2001)

A clock distribution network for microprocessors. - Phillip J. Restle; Timothy G. McNamara; David A. Webber; Peter J. Camporese; Kwok F. Eng; Keith A. Jenkins; David H. Allen; Michael J. Rohn; Michael P. Quaranta; David W. Boerstler; Charles J. Alpert; Craig A. Carter; et al. (IEEE J. Solid State Circuits, 2001)

On-chip wiring design challenges for gigahertz operation. - Alina Deutsch; Paul W. Coteus; Gerard V. Kopcsay; Howard H. Smith; Christopher W. Surovic; Byron Krauter; Daniel C. Edelstein; Phillip J. Restle (Proc. IEEE, 2001)

Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. - Phillip J. Restle; Albert E. Ruehli; Steven G. Walker; George Papadopoulos (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Loop-based interconnect modeling and optimization approach for multi-GHz clock network design. - Xuejue Huang; Phillip J. Restle; Thomas J. Bucelot; Yu Cao 001; Tsu-Jae King 001 (CICC, 2002)

The circuit and physical design of the POWER4 microprocessor. - James D. Warnock; John M. Keaty; John G. Petrovick; Joachim G. Clabes; Charles J. Kircher; Byron Krauter; Phillip J. Restle; Brian A. Zoric; Carl J. Anderson (IBM J. Res. Dev., 2002)

Design of Resonant Global Clock Distributions. - Steven C. Chan; Kenneth L. Shepard; Phillip J. Restle (ICCD, 2003)

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design. - Xuejue Huang; Phillip J. Restle; Thomas J. Bucelot; Yu Cao 001; Tsu-Jae King 001; Chenming Hu (IEEE J. Solid State Circuits, 2003)

Design and implementation of the POWER5 microprocessor. - Joachim G. Clabes; Joshua Friedrich; Mark Sweet; Jack DiLullo; Sam G. Chu; Donald W. Plass; James Dawson; Paul Muench; Larry Powell; Michael S. Floyd; Balaram Sinharoy; Mike Lee; et al. (DAC, 2004)

New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. - Phillip J. Restle; Kenneth L. Shepard (ASYNC, 2005)

Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. - Gerald G. Lopez; Giovanni Fiorenza; Thomas J. Bucelot; Phillip J. Restle; Mary Yvonne Lanzerotti (ACM Great Lakes Symposium on VLSI, 2005)

Uniform-phase uniform-amplitude resonant-load global clock distributions. - Steven C. Chan; Kenneth L. Shepard; Phillip J. Restle (IEEE J. Solid State Circuits, 2005)

A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor. - Michael G. R. Thomson; Phillip J. Restle; Norman K. James (ISSCC, 2006)

Distributed Differential Oscillators for Global Clock Networks. - Steven C. Chan; Kenneth L. Shepard; Phillip J. Restle (IEEE J. Solid State Circuits, 2006)

Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor. - Norman K. James; Phillip J. Restle; Joshua Friedrich; Bill Huott; Bradley D. McCredie (ISSCC, 2007)

IBM POWER6 microprocessor physical design and design methodology. - Rex Berridge; Robert M. Averill III; Arnold E. Barish; Michael A. Bowen; Peter J. Camporese; Jack DiLullo; Peter E. Dudley; Joachim Keinert; David W. Lewis; Robert D. Morel; Thomas E. Rosser; Nicole S. Schwartz; et al. (IBM J. Res. Dev., 2007)

On-chip Timing Uncertainty Measurements on IBM Microprocessors. - Robert L. Franch; Phillip J. Restle; James K. Norman; William V. Huott; Joshua Friedrich; R. Dixon; Steve Weitzel; K. van Goor; Gerard Salem (ITC, 2008)

Ispd2009 clock network synthesis contest. - Cliff N. Sze; Phillip J. Restle; Gi-Joon Nam; Charles J. Alpert (ISPD, 2009)

A Resonant Global Clock Distribution for the Cell Broadband Engine Processor. - Steven C. Chan; Phillip J. Restle; Thomas J. Bucelot; John S. Liberty; Stephen Weitzel; John M. Keaty; Brian K. Flachs; Richard Volant; Peter Kapusta; Jeffrey S. Zimmerman (IEEE J. Solid State Circuits, 2009)

Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. - Joseph N. Kozhaya; Phillip J. Restle; Haifeng Qian (ICCAD, 2011)

POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. - Dieter F. Wendel; Ronald N. Kalla; James D. Warnock; Robert Cargnoni; Sam G. Chu; Joachim G. Clabes; Daniel Dreps; David Hrusecky; Joshua Friedrich; Md. Saiful Islam 004; James A. Kahle; Jens Leenstra; et al. (IEEE J. Solid State Circuits, 2011)

A shorted global clock design for multi-GHz 3D stacked chips. - Liang-Teck Pang; Phillip J. Restle; Matthew R. Wordeman; Joel A. Silberman; Robert L. Franch; Gary W. Maier (VLSIC, 2012)

Subtractive Router for Tree-Driven-Grid Clocks. - Haifeng Qian; Phillip J. Restle; Joseph N. Kozhaya; Clifford L. Gunion (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

On-chip circuit for measuring multi-GHz clock signal waveforms. - Keith A. Jenkins; Phillip J. Restle; P. Z. Wang; D. Hogenmiller; David W. Boerstler; Thomas J. Bucelot (VTS, 2013)

Optimization and modeling of resonant clocking inductors for the POWER8TM microprocessor. - Robert A. Groves; Phillip J. Restle; Alan J. Drake; David Shan; Michael G. R. Thomson (CICC, 2014)

The POWER8TM processor: Designed for big data, analytics, and cloud environments. - Joshua Friedrich; Hung Q. Le; William J. Starke; Jeff Stuecheli; Balaram Sinharoy; Eric J. Fluhr; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; David Hogenmiller; Frank Malgioglio; et al. (ICICDT, 2014)

5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. - Eric J. Fluhr; Joshua Friedrich; Daniel M. Dreps; Victor V. Zyuban; Gregory S. Still; Christopher J. Gonzalez; Allen Hall; David Hogenmiller; Frank Malgioglio; Ryan Nett; Jose Paredes; Juergen Pille; et al. (ISSCC, 2014)

5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor. - Phillip J. Restle; David Shan; David Hogenmiller; Yong Kim; Alan J. Drake; Jason Hibbeler; Thomas J. Bucelot; Gregory S. Still; Keith A. Jenkins; Joshua Friedrich (ISSCC, 2014)

Pacman: driving nonuniform clock grid loads for low-skew robust clock network. - Nancy Y. Zhou; Phillip J. Restle; Joseph N. Palumbo; Joseph N. Kozhaya; Haifeng Qian; Zhuo Li 001; Charles J. Alpert; Cliff C. N. Sze (SLIP, 2014)

Resonant clock mega-mesh for the IBM z13TM. - David Shan; Phillip J. Restle; Doug Malone; Robert A. Groves; Eric Lai; Michael Koch 009; Jason Hibbeler; Yong Kim; Christos Vezyrtzis; Jan Feder; David Hogenmiller; Thomas J. Bucelot (VLSIC, 2015)

IBM POWER8 circuit design and energy optimization. - Victor V. Zyuban; Joshua Friedrich; Daniel M. Dreps; Jürgen Pille; Donald W. Plass; Phillip J. Restle; Zeynep Toprak Deniz; Matthew M. Ziegler; Sam G. Chu; Md. Saiful Islam 004; James D. Warnock; Bob Philhower; et al. (IBM J. Res. Dev., 2015)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

Thermal analysis of multi-layer functional 3D logic stacks. - Michael Scheuermann; Shurong Tian; Raphael Robertazzi; Matthew R. Wordeman; C. Bergeron; H. Jacobson; Phillip J. Restle; Joel Silberman; Christy Tyberg (3DIC, 2016)

26.2 Power supply noise in a 22nm z13™ microprocessor. - Pierce I-Jen Chuang; Christos Vezyrtzis; Divya Pathak; Richard F. Rizzolo; Tobias Webel; Thomas Strach; Otto A. Torreiter; Preetham Lobo; Alper Buyuktosunoglu; Ramon Bertran; Michael S. Floyd; Malcolm S. Ware; et al. (ISSCC, 2017)

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. - Michael S. Floyd; Phillip J. Restle; Michael A. Sperling; Pawel Owczarczyk; Eric J. Fluhr; Joshua Friedrich; Paul Muench; Timothy Diemoz; Pierce Chuang; Christos Vezyrtzis (ISSCC, 2017)

EE5: Lessons learned - Great circuits that didn't work - (Oops, if only i had known!). - Phillip J. Restle; Kostas Doris; Vivek De; Paul Ferguson (ISSCC, 2018)

Session 7 overview: Neuromorphic, clocking and security circuits: Digital circuits subcommittee. - Youngmin Shin; Phillip J. Restle; Edith Beigné (ISSCC, 2018)

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. - Christos Vezyrtzis; Thomas Strach; Pierce I-Jen Chuang; Preetham Lobo; Richard F. Rizzolo; Tobias Webel; Pawel Owczarczyk; Alper Buyuktosunoglu; Ramon Bertran; David T. Hui; Susan M. Eickhoff; Michael S. Floyd; et al. (ISSCC, 2018)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems. - Christopher J. Berry; David Wolpert 001; Christos Vezyrtzis; Richard F. Rizzolo; Sean M. Carey; Yaniv Maroz; Hunter F. Shi; Dureseti Chidambarrao; Christian Jacobi 002; Anthony Saporito; Thomas Strach; Alper Buyuktosunoglu; et al. (IEEE J. Solid State Circuits, 2019)

Deterministic Frequency Boost and Voltage Enhancements on the POWER10TM Processor. - Brian T. Vanderpool; Phillip J. Restle; Eric J. Fluhr; Gregory S. Still; Frank Campisano; Ian Carmichael; Eric Marz; Rahul Batra; Richard L. Willaman (ISSCC, 2022)

Deterministic Frequency and Voltage Enhancements on the POWER10 Processor. - Brian T. Vanderpool; Phillip J. Restle; Eric Fluhr; Gregory S. Still; Francesco A. Campisano; Ian Charmichael; Eric Marz; Rahul Batra; Richard L. Willaman (IEEE J. Solid State Circuits, 2023)

8.1 Dynamic Guard-Band Features of the IBM zNext System. - Tobias Webel; Phillip J. Restle; Ramon Bertran; Alper Buyuktosunoglu; Sean M. Carey; Alejandro Cook; Karl Anderson; Michael Romain; Thomas Strach; Pradeep Bhadravati Parashurama; Aishwarya Tadkase; Rahman Abber Tahir; et al. (ISSCC, 2025)