Congestion Driven Quadratic Placement. - Phiroze N. Parakh; Richard B. Brown; Karem A. Sakallah (DAC, 1998)

Overview of complementary GaAs technology for high-speed VLSI circuits. - Richard B. Brown; Bruce Bernhardt; M. LaMacchia; J. Abrokwah; Phiroze N. Parakh; Todd D. Basso; Spencer M. Gold; S. Stetson; Claude R. Gauthier; D. Foster; B. Crawforth; T. McQuire; et al. (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Crosstalk constrained global route embedding. - Phiroze N. Parakh; Richard B. Brown (ISPD, 1999)

CGaAs PowerPC FXU. - Alan J. Drake; Todd D. Basso; Spencer M. Gold; Keith L. Kraver; Phiroze N. Parakh; Claude R. Gauthier; P. Sean Stetson; Richard B. Brown (DAC, 2000)

Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement. - Navaratnasothie Selvakkumaran; Phiroze N. Parakh; George Karypis (SLIP, 2003)

Benchmarking for large-scale placement and beyond. - Saurabh N. Adya; Mehmet Can Yildiz; Igor L. Markov; Paul Villarrubia; Phiroze N. Parakh; Patrick H. Madden (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004)

A robust approach to lithography friendly design implementation. - Phiroze N. Parakh; Shankar Krishnamoorthy (ISPD, 2008)