A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. - Meng-Fan Chang; Shu-Meng Yang; Chih-Wei Liang; Chih-Chyuang Chiang; Pi-Feng Chiu; Ku-Feng Lin; Yuan-Hua Chu; Wen-Chin Wu; Hiroyuki Yamauchi (ISSCC, 2010)

Noise-Immune Embedded NAND-ROM Using a Dynamic Split Source-Line Scheme for VDDmin and Speed Improvements. - Meng-Fan Chang; Shu-Meng Yang; Chih-Wei Liang; Chih-Chyuang Chiang; Pi-Feng Chiu; Ku-Feng Lin (IEEE J. Solid State Circuits, 2010)

Challenges and trends in low-power 3D die-stacked IC designs using RAM, memristor logic, and resistive memory (ReRAM). - Meng-Fan Chang; Pi-Feng Chiu; Wei-Cheng Wu; Ching-Hao Chuang; Shyh-Shyuan Sheu (ASICON, 2011)

Circuit design challenges in embedded memory and resistive RAM (RRAM) for mobile SoC and 3D-IC. - Meng-Fan Chang; Pi-Feng Chiu; Shyh-Shyuan Sheu (ASP-DAC, 2011)

A 4Mb embedded SLC resistive-RAM macro with 7.2ns read-write random-access time and 160ns MLC-access capability. - Shyh-Shyuan Sheu; Meng-Fan Chang; Ku-Feng Lin; Che-Wei Wu; Yu-Sheng Chen; Pi-Feng Chiu; Chia-Chen Kuo; Yih-Shan Yang; Pei-Chia Chiang; Wen-Pin Lin; Che-He Lin; Heng-Yuan Lee; et al. (ISSCC, 2011)

Endurance-aware circuit designs of nonvolatile logic and nonvolatile sram using resistive memory (memristor) device. - Meng-Fan Chang; Ching-Hao Chuang; Min-Ping Chen; Lai-Fu Chen; Hiroyuki Yamauchi; Pi-Feng Chiu; Shyh-Shyuan Sheu (ASP-DAC, 2012)

Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications. - Pi-Feng Chiu; Meng-Fan Chang; Che-Wei Wu; Ching-Hao Chuang; Shyh-Shyuan Sheu; Yu-Sheng Chen; Ming-Jinn Tsai (IEEE J. Solid State Circuits, 2012)

A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes. - Meng-Fan Chang; Shyh-Shyuan Sheu; Ku-Feng Lin; Che-Wei Wu; Chia-Chen Kuo; Pi-Feng Chiu; Yih-Shan Yang; Yu-Sheng Chen; Heng-Yuan Lee; Chen-Hsin Lien; Frederick T. Chen; Keng-Li Su; et al. (IEEE J. Solid State Circuits, 2013)

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. - Yunsup Lee; Brian Zimmer; Andrew Waterman; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Henry Cook; Rimas Avizienis; et al. (Hot Chips Symposium, 2015)

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (VLSIC, 2015)

A Differential 2R Crosspoint RRAM Array With Zero Standby Current. - Pi-Feng Chiu; Borivoje Nikolic (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A double-tail sense amplifier for low-voltage SRAM in 28nm technology. - Pi-Feng Chiu; Brian Zimmer; Borivoje Nikolic (A-SSCC, 2016)

Reprogrammable redundancy for cache Vmin reduction in a 28nm RISC-V processor. - Brian Zimmer; Pi-Feng Chiu; Borivoje Nikolic; Krste Asanovic (A-SSCC, 2016)

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC. - Ben Keller; Martin Cochet; Brian Zimmer; Yunsup Lee; Milovan Blagojevic; Jaehwa Kwak; Alberto Puggelli; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (ESSCIRC, 2016)

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. - Brian Zimmer; Yunsup Lee; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Ben Keller; Steven Bailey; Milovan Blagojevic; Pi-Feng Chiu; Hanh-Phuc Le; Po-Hung Chen; Nicholas Sutardja; et al. (IEEE J. Solid State Circuits, 2016)

An Agile Approach to Building RISC-V Microprocessors. - Yunsup Lee; Andrew Waterman; Henry Cook; Brian Zimmer; Ben Keller; Alberto Puggelli; Jaehwa Kwak; Ruzica Jevtic; Stevo Bailey; Milovan Blagojevic; Pi-Feng Chiu; Rimas Avizienis; et al. (IEEE Micro, 2016)

A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI. - Ben Keller; Martin Cochet; Brian Zimmer; Jaehwa Kwak; Alberto Puggelli; Yunsup Lee; Milovan Blagojevic; Stevo Bailey; Pi-Feng Chiu; Daniel Palmer Dabbelt; Colin Schmidt 001; Elad Alon; et al. (IEEE J. Solid State Circuits, 2017)

Reprogrammable Redundancy for SRAM-Based Cache Vmin Reduction in a 28-nm RISC-V Processor. - Brian Zimmer; Pi-Feng Chiu; Borivoje Nikolic; Krste Asanovic (IEEE J. Solid State Circuits, 2017)

Improving Noise Tolerance of Hardware Accelerated Artificial Neural Networks. - Wen Ma; Minghai Qin; Won Ho Choi; Pi-Feng Chiu; Martin Lueker-Boden (ICMLA, 2018)

An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS. - Pi-Feng Chiu; Christopher Celio; Krste Asanovic; David A. Patterson 001; Borivoje Nikolic (VLSI Circuits, 2018)

Bottom-up Memory Design Techniques for Energy-Efficient and Resilient Computing - Pi-Feng Chiu (2018)

Non-Volatile Memory Array Based Quantization- and Noise-Resilient LSTM Neural Networks. - Wen Ma; Pi-Feng Chiu; Won Ho Choi; Minghai Qin; Daniel Bedau; Martin Lueker-Boden (ICRC, 2019)

A Binarized Neural Network Accelerator with Differential Crosspoint Memristor Array for Energy-Efficient MAC Operations. - Pi-Feng Chiu; Won Ho Choi; Wen Ma; Minghai Qin; Martin Lueker-Boden (ISCAS, 2019)

BROOM: An Open-Source Out-of-Order Processor With Resilient Low-Voltage Operation in 28-nm CMOS. - Christopher Celio; Pi-Feng Chiu; Krste Asanovic; Borivoje Nikolic; David A. Patterson 001 (IEEE Micro, 2019)

An In-Flash Binary Neural Network Accelerator with SLC NAND Flash Array. - Won Ho Choi; Pi-Feng Chiu; Wen Ma; Gertjan Hemink; Tung Thanh Hoang; Martin Lueker-Boden; Zvonimir Bandic (ISCAS, 2020)

A Mott Insulator-Based Oscillator Circuit for Reservoir Computing. - Wen Ma; Tyler Hennen; Martin Lueker-Boden; Rick Galbraith; Jonas Goode; Won Ho Choi; Pi-Feng Chiu; Jonathan A. J. Rupp; Dirk J. Wouters; Rainer Waser; Daniel Bedau (ISCAS, 2020)

A Dual-Core RISC-V Vector Processor With On-Chip Fine-Grain Power Management in 28-nm FD-SOI. - John Charles Wright; Colin Schmidt 001; Ben Keller; Daniel Palmer Dabbelt; Jaehwa Kwak; Vighnesh Iyer; Nandish Mehta; Pi-Feng Chiu; Stevo Bailey; Krste Asanovic; Borivoje Nikolic (IEEE Trans. Very Large Scale Integr. Syst., 2020)