Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture. - Roberto Nonis; Nicola Da Dalt; Pierpaolo Palestri; Luca Selmi (IEEE J. Solid State Circuits, 2005)

Monte-Carlo simulations of hot-carrier effectes and photon-emission in MOS devices. - Pierpaolo Palestri (2005)

The Monte Carlo approach to transport modeling in deca-nanometer MOSFETs. - Enrico Sangiorgi; Pierpaolo Palestri; David Esseni; Claudio Fiegna; Luca Selmi (ESSCIRC, 2007)

A Design Methodology for MOS Current-Mode Logic Frequency Dividers. - Roberto Nonis; Enzo Palumbo; Pierpaolo Palestri; Luca Selmi (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET. - Davide Ponton; Pierpaolo Palestri; David Esseni; Luca Selmi; Marc Tiebout; Bertrand Parvais; Gerhard Knoblinger (ISCAS, 2008)

Comprehensive Behavioral Modeling of Conventional and Dual-Tuning PLLs. - Luca Bizjak; Nicola Da Dalt; Peter Thurner; Roberto Nonis; Pierpaolo Palestri; Luca Selmi (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Assessment of the impact of technology scaling on the performance of LC-VCOs. - Davide Ponton; Gerhard Knoblinger; Andreas Roithmeier; Marc Tiebout; Michael Fulde; Pierpaolo Palestri (ESSCIRC, 2009)

Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices. - Davide Ponton; Pierpaolo Palestri; David Esseni; Luca Selmi; Marc Tiebout; Bertrand Parvais; Domagoj Siprak; Gerhard Knoblinger (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

A numerical model for the oscillation frequency, the amplitude and the phase-noise of MOS-current-mode-logic ring oscillators. - Michele Nocente; Donald Fontanelli; Pierpaolo Palestri; Roberto Nonis; David Esseni; Luca Selmi (Int. J. Circuit Theory Appl., 2010)

LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology. - Davide Ponton; Gerhard Knoblinger; Andreas Roithmeier; Federico Cernoia; Marc Tiebout; Michael Fulde; Pierpaolo Palestri (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

A Multi-Subband Monte Carlo study of electron transport in strained SiGe n-type FinFETs. - Daniel Lizzit; Pierpaolo Palestri; David Esseni; Francesco Conzatti; Luca Selmi (ESSDERC, 2012)

Microscopic scale characterization and modeling of transistor degradation under HC stress. - Yoann Mamy Randriamihaja; Vincent Huard; Xavier Federspiel; Alban Zaka; Pierpaolo Palestri; Denis Rideau; David Roy 001; Alain Bravaix (Microelectron. Reliab., 2012)

On the optimization of SiGe and III-V compound hetero-junction Tunnel FET devices. - Alberto Revelant; Pierpaolo Palestri; Patrik Osgnach; Daniel Lizzit; Luca Selmi (ESSDERC, 2013)

On the response of nanoelectrode capacitive biosensors to DNA and PNA strands. - Federico Pittino; Federico Passerini; Pierpaolo Palestri; Luca Selmi; Frans Widdershoven (IWASI, 2013)

Two dimensional quantum mechanical simulation of low dimensional tunneling devices. - Cem Alper; Pierpaolo Palestri; Livio Lattanzio; Jose L. Padilla; Adrian M. Ionescu (ESSDERC, 2014)

Analysis of TFET based 6T SRAM cells implemented with state of the art silicon nanowires. - Sebastiano Strangio; Pierpaolo Palestri; David Esseni; Luca Selmi; Felice Crupi (ESSDERC, 2014)

Graphene base transistors with optimized emitter and dielectrics. - Stefano Venica; Francesco Driussi; Pierpaolo Palestri; Luca Selmi (MIPRO, 2014)

Improved surface roughness modeling and mobility projections in thin film MOSFETs. - O. Badami; Enrico Caruso; Daniel Lizzit; David Esseni; Pierpaolo Palestri; Luca Selmi (ESSDERC, 2015)

State-of-the-art semi-classical Monte Carlo method for carrier transport in nanoscale transistors. - Pierpaolo Palestri; Enrico Caruso; Francesco Driussi; David Esseni; Daniel Lizzit; Patrik Osgnach; Stefano Venica; Luca Selmi (MIPRO, 2015)

Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall. - Andrea Cossettini; Andrea Cristofoli; Werner Grollitsch; Lino Alves; Roberto Nonis; Luca Della Ricca; Pierpaolo Palestri; Luca Selmi (RTSI, 2015)

Design and implementation of switched coil LC-VCOs in the GHz range using the self-inductance technique. - Federico Cernoia; Davide Ponton; Pierpaolo Palestri; Peter Thurner; Nicola Da Dalt; Giulio Cecco; Luca Selmi (Int. J. Circuit Theory Appl., 2015)

Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Roberto Nonis; Pierpaolo Palestri (APCCAS, 2016)

Impact of device geometry of the fin Electron-Hole Bilayer Tunnel FET. - Cem Alper; Jose L. Padilla; Pierpaolo Palestri; Adrian M. Ionescu (ESSDERC, 2016)

Performance study of strained III-V materials for ultra-thin body transistor applications. - Martin Rau; Troels Markussen; Enrico Caruso; David Esseni; Elena Gnani; Antonio Gnudi; Petr A. Khomyakov; Mathieu Luisier; Patrik Osgnach; Pierpaolo Palestri; Susanna Reggiani; Andreas Schenk; et al. (ESSDERC, 2016)

Design of a transmitter for high-speed serial interfaces in automotive micro-controller. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Roberto Nonis; Pierpaolo Palestri (MIPRO, 2016)

Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM. - Gia Vinh Luong; Sebastiano Strangio; Andreas T. Tiedemann; Patric Bernardy; Stefan Trellenkamp; Pierpaolo Palestri; Siegfried Mantl; Qing-Tai Zhao (ESSDERC, 2017)

Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm. - Andrea Bandiziol; Werner Grollitsch; Francesco Brandonisio; Matteo Bassi; Roberto Nonis; Pierpaolo Palestri (ISCAS, 2018)

Sub-mW multi-Gbps chip-to-chip communication Links for Ultra-Low Power IoT end-nodes. - Martino Dazzi; Pierpaolo Palestri; Davide Rossi; Andrea Bandiziol; Igor Loi; David E. Bellasi; Luca Benini (ISCAS, 2018)

Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE. - Andrea Bandiziol; Werner Grollitsch; Giovanni Steffan; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers. - Dylan D'Ampolo; Andrea Bandiziol; Davide Menin; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (APCCAS, 2019)

A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces. - Alessio Cortiula; Martino Dazzi; Mattia Marcon; Davide Menin; Marco Scapol; Andrea Bandiziol; Andrea Cristofoli; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (MIPRO, 2019)

Ultra-High Frequency (500 MHz) Capacitance Spectroscopy for Nanobiosensing. - Andrea Cossettini; Denis Brandalise; Pierpaolo Palestri; Alessandro Bertacchini; Michele Ramponi; Frans Widdershoven; Luca Benini; Luca Selmi (IEEE SENSORS, 2020)

An Energy-Efficient Low-Voltage Swing Transceiver for mW-Range IoT End-Nodes. - Hayate Okuhara; Ahmed Elnaqib; Davide Rossi; Alfio Di Mauro; Philipp Mayer; Pierpaolo Palestri; Luca Benini (ISCAS, 2020)

Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications. - Davide Menin; Andrea Bandiziol; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Fully-Integrated 5mW, 0.8Gbps Energy-Efficient Chip-to-Chip Data Link for Ultra-Low-Power IoT End-Nodes in 65-nm CMOS. - Hayate Okuhara; Ahmed Elnaqib; Martino Dazzi; Pierpaolo Palestri; Simone Benatti; Luca Benini; Davide Rossi (CoRR, 2021)

Sensitivity, Noise and Resolution in a BEOL-Modified Foundry-Made ISFET with Miniaturized Reference Electrode for Wearable Point-of-Care Applications. - Francesco Bellando; Leandro Julian Mele; Pierpaolo Palestri; Junrui Zhang 001; Adrian Mihai Ionescu; Luca Selmi (Sensors, 2021)

A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS. - Hayate Okuhara; Ahmed Elnaqib; Martino Dazzi; Pierpaolo Palestri; Simone Benatti; Luca Benini; Davide Rossi (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation. - Pierpaolo Palestri; Ahmed Elnaqib; Davide Menin; Klaid Shyti; Francesco Brandonisio; Andrea Bandiziol; Davide Rossi; Roberto Nonis (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Multiphysics Finite-Element Modeling of the Neuron/Electrode Electrodiffusive Interaction. - Federico Leva; Claudio Verardo; Leandro Julian Mele; Pierpaolo Palestri; Luca Selmi (IEEE SENSORS, 2022)

Synchrotron Radiation Study of Gain, Noise, and Collection Efficiency of GaAs SAM-APDs with Staircase Structure. - Matija Colja; Marco Cautero; Ralf-Hendrik Menk; Pierpaolo Palestri; Alessandra Gianoncelli; Matias Antonelli; Giorgio Biasiol; Simone Dal Zilio; Tereza Steinhartova; Camilla Nichetti; Fulvia Arfelli; Dario De Angelis; et al. (Sensors, 2022)

Identification of Axon Bendings in Neurons by Multiphysics FEM Simulations of High-Density MEA Extracellular Recordings. - Federico Leva; Andrea Corna; Paul Werginz; Pierpaolo Palestri; Günter Zeck; Luca Selmi (SENSORS, 2023)

Mitigation of Electrical/Ionic Interference in Iontronic Neurostimulation/Neurosensing Platforms: A Simulation Study. - Jacopo Nicolini; Federico Leva; Pierpaolo Palestri; Luca Selmi (SENSORS, 2023)

A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces. - Alessio Cortiula; Davide Menin; Andrea Bandiziol; Werner Grollitsch; Roberto Nonis; Pierpaolo Palestri (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

From Finite Element Simulations to Equivalent Circuit Models of Extracellular Neuronal Recording Systems Based on Planar and Mushroom Electrodes. - Federico Leva; Claudio Verardo; Pierpaolo Palestri; Luca Selmi (IEEE Trans. Biomed. Eng., 2024)

Impact of Gate Metal Work Function on 1/f Noise in RMG MOSFETs. - R. Asanovski; Hiroaki Arimura; J. Ganguly; Pierpaolo Palestri; Alexander Grill; Ben Kaczer; Naoto Horiguchi; Luca Selmi; Jacopo Franco (IRPS, 2025)