A new two-step ΣΔ architecture column-parallel ADC for CMOS image sensor. - Pierre Bisiaux; Caroline Lelandais-Perrault; Anthony Kolar; Philippe Bénabès; Filipe Vinci dos Santos (SBCCI, 2016)

A 14-b two-step inverter-based ΣΔ ADC for CMOS image sensor. - Pierre Bisiaux; Caroline Lelandais-Perrault; Anthony Kolar; Philippe Bénabès; Filipe Vinci dos Santos (NEWCAS, 2017)

Experimental Demonstration of a 65 nm Integrated CMOS Waveform Generator for 5G sub-6GHz Standard. - Pierre Bisiaux; Francois Rivet; Yoan Veyrac; Yann Deval (ICECS, 2018)

All-Digital Phase-Locked Loop Arrays: Investigation of Synchronisation and Jitter Performance through FPGA Prototyping. - Eugene Koskin; Pierre Bisiaux; Dimitri Galayko; Elena Blokhina (NEWCAS, 2019)

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process. - Pierre Bisiaux; Elena Blokhina; Eugene Koskin; Teerachot Siriburanon; Dimitri Galayko (ECCTD, 2020)

FPGA Validation of Event-Driven ADPLL. - Eugene Koskin; Pierre Bisiaux; Dimitri Galayko; Elena Blokhina (ECCTD, 2020)

All Digital Phase-Locked Loop Networks for Clock Generation and Distribution: Network Stability, Convergence and Performance. - Eugene Koskin; Pierre Bisiaux; Dimitri Galayko; Elena Blokhina (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Jitter Optimisation in a Generalised All-Digital Phase-Locked Loop Model. - Eugene Koskin; Pierre Bisiaux; Dimitri Galayko; Elena Blokhina (IEEE Trans. Circuits Syst. II Express Briefs, 2021)